// Lab 2 part 1
// USE LEDREG.BIT

#include <reg51.h>
#include <stdlib.h>
unsigned char xdata *ledaddress;

// constant 
unsigned long bits_32;
unsigned int bits_16;

// send data
unsigned long send1;
unsigned int send2;


// input x & y

sbit Port0 = P0 ^0;
sbit Port1 = P0 ^1;
sbit Port2 = P0 ^2;
sbit Port3 = P0 ^3;
sbit Port4 = P0 ^4;
sbit Port5 = P0 ^5;
sbit Port6 = P0 ^6;
sbit Port7 = P0 ^7;
sbit Port8 = P2 ^0;
sbit Port9 = P2 ^1;
sbit Port10 = P2 ^2;
sbit Port11 = P2 ^3;
sbit Port12 = P2 ^4;
sbit Port13 = P2 ^5;
sbit Port14 = P2 ^6;
sbit Port15 = P2 ^7;


bit rise_edge;
bit En;
int temp;
sbit clk = P1 ^ 1; // pin 8
sbit data_out = P1 ^ 2; // pin 9 			


// -------------- clock input into PS/2 mouse port
void generate_clk (void) interrupt 1 using 1 { // timer 0
//	if (temp < 22)	{
		if (clk == 1) {
				clk = 0;
		}
		else {
				rise_edge = 1;
				clk = 1;
		}
//	}	
//	temp = temp + 1;
//	if (temp == 22) clk = 0;
//	if (temp == 26) {
//		temp = 0;
//		clk = 1;
//	}

}


// -------------------------------------------
/*
void time_out (void) interrupt 3 using 1 { // timer 1
	if (flag++ == 1) {
  	 ET0 = 1;
  	 ET1 = 0; // reset after timeout
   }
}
*/


//------------------------- new frame from FPGA
void Newframe ( void ) interrupt 0 using 0 {

// connect p3.2 with the output from FPGA

En = 1;

// reset En when do the sending
}
//------------------------------------------------------

void init () {

	TMOD = 0x22;
	TCON = 0x50;
	TH0 = 169;
	TH1 = 80;
	temp = 0;
	

	data_out = 1;
	rise_edge = 0;
	clk = 1;
	EA = 1;
    ET0 = 1;
	ET1 = 0;
  
	// packets initialize - these bits never change
	bits_32 = 0x00200410;  // 32 bits first packet
	bits_16 = 0x0821;     // 12 bit 2nd packet .  A total of 44 bit packets


	// for testing purpose
 Port0 = 1;
 Port1 = 0;
 Port2 = 1;
 Port3 = 0;
 Port4 = 1;
  Port5 = 0;
  Port6 = 1;
  Port7 = 1;
  Port8 = 1;
  Port9 = 0;
  Port10 = 1;
  Port11 = 0;
  Port12 = 1;
  Port13 = 1;
  Port14 = 0;
  Port15 = 0;

	// EX0 = 1;  // for interrupt of new frame ; it should be turn on when runs real
}

// --------------------- load reg after there's a frame

void new_load(void) { 	
unsigned long temp1 = 0;
bit Yparity, Xparity;

Xparity = (Port0 ^ Port1 ^ Port2 ^ Port3 ^ Port4 ^ Port5 ^ Port6 ^ Port7);
Yparity = (Port8 ^ Port9 ^ Port10 ^ Port11 ^ Port12 ^ Port13 ^ Port14 ^ Port15);
temp1 = ((temp1 | Yparity) << 8) | P2; // take cares parity & y
temp1 = ((((temp1 << 3) | Xparity) << 8) | P0) << 12;    // take cares parity & x
send1 = bits_32 | temp1;  
send2 = bits_16; 
}
//-------------------------------------
//}

void main() {
     int i;

   	 init();

En = 1;
     while (1) { // all programs run forever

	 	 i = 0;
		 En = 1; // just for testing
		 if (En) {				// if something to send
			new_load();			
			En = 0; 				// reset it 			
			clk = 1;
			send1 = send1 >> 1;
			data_out = 0; // 1st bit - force to low to start transmitt data
			ET0 = 1;  // make sure that the clock egde go down after data_out = first bit of sending data.  
		 }
		 if (rise_edge) {	// rising edge						
			 while (i < 44) {			 
				if (( i < 32) && rise_edge) { // 32 bit of data				
					data_out = send1 & 0x00000001;			
					rise_edge = 0;					
					send1 = send1 >> 1;
					i++;
				}
			//	if ((i == 10) || (i == 21) || (i == 32)) {				
					// after clk == 0, stay there until after time_out, it will go up again (time_out ~172micro sec)
			//		flag = 0;
			//		ET0 = 0;  
			//		ET1 = 1;  // set the 2nd interrupt to time out time between packet.
					
			//	}

				if (( 31 < i) && (i < 44) && rise_edge) { // 12 bit of data - total is 44 bit of data
					data_out = send2 & 0x00000001;
					send2 = send2 >> 1;
					rise_edge = 0;
					i++;
				}
				if (i == 44) {
					ET0 = 0; // stop clock until next frame
					clk = 1; // turns it back to normal position
				}
			}
		}  				
		

	}

}