# # time_sim.xmm created by ngd2edif on Mon May 01 16:59:18 2000 # # This file contains information on the initial contents of each # RAM primitive. Depending on your simulation interface, the data # in this file might be required to correctly model the initial # contents of RAM components. (Some simulators will extract this # information directly from the EDIF netlist.) # # Each line below represents a single RAM primitive in the EDIF # netlist. There are three tokens on each line, separated by white # space. The first token is the primitive type, and matches a # symbol from the simprims library. The second token is the full # hierarchical instance name for the primitive. The third token is # the initial value for that primitive, expressed as a hexadecimal # number (the same convention used for INIT properties). # X_RAMS16 H1/H4/L1/MEM0_0/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM0_0/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM0_1/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM0_1/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM0_2/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM0_2/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM0_3/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM0_3/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM0_4/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM0_4/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM0_5/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM0_5/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM0_6/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM0_6/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM0_7/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM0_7/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM1_0/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM1_0/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM1_1/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM1_1/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM1_2/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM1_2/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM1_3/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM1_3/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM1_4/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM1_4/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM1_5/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM1_5/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM1_6/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM1_6/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM1_7/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM1_7/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM2_0/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM2_0/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM2_1/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM2_1/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM2_2/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM2_2/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM2_3/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM2_3/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM2_4/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM2_4/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM2_5/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM2_5/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM2_6/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM2_6/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM2_7/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM2_7/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM3_0/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM3_0/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM3_1/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM3_1/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM3_2/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM3_2/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM3_3/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM3_3/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM3_4/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM3_4/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM3_5/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM3_5/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM3_6/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM3_6/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM3_7/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM3_7/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM4_0/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM4_0/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM4_1/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM4_1/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM4_2/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM4_2/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM4_3/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM4_3/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM4_4/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM4_4/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM4_5/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM4_5/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM4_6/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM4_6/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM4_7/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM4_7/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM5_0/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM5_0/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM5_1/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM5_1/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM5_2/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM5_2/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM5_3/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM5_3/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM5_4/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM5_4/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM5_5/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM5_5/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM5_6/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM5_6/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM5_7/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM5_7/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM6_0/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM6_0/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM6_1/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM6_1/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM6_2/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM6_2/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM6_3/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM6_3/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM6_4/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM6_4/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM6_5/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM6_5/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM6_6/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM6_6/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM6_7/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM6_7/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM7_0/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM7_0/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM7_1/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM7_1/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM7_2/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM7_2/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM7_3/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM7_3/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM7_4/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM7_4/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM7_5/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM7_5/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM7_6/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM7_6/X_RAMD16 0x0000 X_RAMS16 H1/H4/L1/MEM7_7/X_RAMS16 0x0000 X_RAMD16 H1/H4/L1/MEM7_7/X_RAMD16 0x0000