ngdbuild -p xc4010xl-3-pc84 -uc vgacam.ucf -dd .. D:\CAM\VGACAM\vgacam.EDN vgacam.ngd ngdbuild: version C.21 Copyright (c) 1995-1999 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -p xc4010xl-3-pc84 -uc vgacam.ucf -dd .. D:\CAM\VGACAM\vgacam.EDN vgacam.ngd Launcher: Executing edif2ngd "D:\CAM\VGACAM\vgacam.EDN" "d:\cam\vgacam\xproj\ver1\vgacam.ngo" edif2ngd: version C.21 Copyright (c) 1995-1999 Xilinx, Inc. All rights reserved. Writing the design to "d:/cam/vgacam/xproj/ver1/vgacam.ngo"... Reading NGO file "d:/cam/vgacam/xproj/ver1/vgacam.ngo" ... Reading component libraries for design expansion... Running LogiBLOX expansion on symbol "L1"... Running LogiBLOX expansion on symbol "L2"... Running LogiBLOX expansion on symbol "L3"... Launcher: "EQUALS.ngo" is up to date. Loading design module "d:\cam\vgacam\xproj\ver1\EQUALS.ngo"... Running LogiBLOX expansion on symbol "L1"... Running LogiBLOX expansion on symbol "L13"... Running LogiBLOX expansion on symbol "L14"... Running LogiBLOX expansion on symbol "L15"... Running LogiBLOX expansion on symbol "L27"... Running LogiBLOX expansion on symbol "L30"... Running LogiBLOX expansion on symbol "L31"... Running LogiBLOX expansion on symbol "L32"... Running LogiBLOX expansion on symbol "L33"... Launcher: "CAMERA_TEST.ngo" is up to date. Loading design module "d:\cam\vgacam\xproj\ver1\CAMERA_TEST.ngo"... Running LogiBLOX expansion on symbol "L1"... Running LogiBLOX expansion on symbol "L2"... Running LogiBLOX expansion on symbol "L3"... Running LogiBLOX expansion on symbol "L4"... Running LogiBLOX expansion on symbol "L7"... Launcher: "MEMCONTROL.ngo" is up to date. Loading design module "d:\cam\vgacam\xproj\ver1\MEMCONTROL.ngo"... Running LogiBLOX expansion on symbol "L1"... Running LogiBLOX expansion on symbol "L11"... Running LogiBLOX expansion on symbol "L12"... Running LogiBLOX expansion on symbol "L4"... Launcher: "SYNCGEN.ngo" is up to date. Loading design module "d:\cam\vgacam\xproj\ver1\SYNCGEN.ngo"... Launcher: Executing xnf2ngd -p xc4000xl "D:\CAM\VGACAM\BLANKPIXEL.xnf" "d:\cam\vgacam\xproj\ver1\BLANKPIXEL.ngo" xnf2ngd: version C.21 Copyright (c) 1995-1999 Xilinx, Inc. All rights reserved. using XNF gate model reading XNF file "D:/CAM/VGACAM/BLANKPIXEL.xnf" ... Writing NGO file "d:/cam/vgacam/xproj/ver1/BLANKPIXEL.ngo" ... Loading design module "d:\cam\vgacam\xproj\ver1\BLANKPIXEL.ngo"... Launcher: "BANKSELECT.ngo" is up to date. Loading design module "d:\cam\vgacam\xproj\ver1\BANKSELECT.ngo"... Launcher: "LASERSPOT.ngo" is up to date. Loading design module "d:\cam\vgacam\xproj\ver1\LASERSPOT.ngo"... Launcher: Executing xnf2ngd -p xc4000xl "D:\CAM\VGACAM\CROSSHAIRS.xnf" "d:\cam\vgacam\xproj\ver1\CROSSHAIRS.ngo" xnf2ngd: version C.21 Copyright (c) 1995-1999 Xilinx, Inc. All rights reserved. using XNF gate model reading XNF file "D:/CAM/VGACAM/CROSSHAIRS.xnf" ... Writing NGO file "d:/cam/vgacam/xproj/ver1/CROSSHAIRS.ngo" ... Loading design module "d:\cam\vgacam\xproj\ver1\CROSSHAIRS.ngo"... Annotating constraints to design from file "vgacam.ucf" ... Checking timing specifications ... Checking expanded design ... WARNING:NgdHelpers:357 - clock net "H2/$Net00002_" has non-clock connections WARNING:NgdHelpers:357 - clock net "CLK" has non-clock connections WARNING:NgdHelpers:334 - logical net "VCCX" has no load WARNING:NgdHelpers:334 - logical net "GNDX" has no load NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 4 Writing NGD file "vgacam.ngd" ... Writing NGDBUILD log file "vgacam.bld"... NGDBUILD done. ================================================== map -p xc4010xl-3-pc84 -o map.ncd vgacam.ngd vgacam.pcf map: version C.21 Copyright (c) 1995-1999 Xilinx, Inc. All rights reserved. Reading NGD file "vgacam.ngd"... Using target part "4010xlpc84-3". MAP xc4000xl directives: Partname = "xc4010xl-3-pc84". Covermode = "area". Pack Unrelated Logic into CLBs targeting 100% of CLB resources. Processing logical timing constraints... Verifying F/HMAP validity based on pre-trimmed logic... Removing unused logic... Packing logic in CLBs... Running cover... Undirected packing... Running physical design DRC... Design Summary: Number of errors: 0 Number of warnings: 4 Number of CLBs: 233 out of 400 58% CLB Flip Flops: 202 CLB Latches: 0 4 input LUTs: 249 (1 used as route-throughs) 3 input LUTs: 89 (48 used as route-throughs) Dual Port RAMs: 64 Number of bonded IOBs: 52 out of 65 80% IOB Flops: 31 IOB Latches: 0 Number of BUFGLSs: 3 out of 8 37% Number of MD1: 1 out of 1 100% Total equivalent gate count for design: 11640 Additional JTAG gate count for IOBs: 2544 Writing design file "map.ncd"... Removed Logic Summary: 228 block(s) removed 27 block(s) optimized away 228 signal(s) removed Mapping completed. See MAP report file "map.mrp" for details. ================================================== par -w -ol 2 -d 0 map.ncd vgacam.ncd vgacam.pcf PAR: Xilinx Place And Route C.21. Copyright (c) 1995-1999 Xilinx, Inc. All rights reserved. Constraints file: vgacam.pcf Loading device database for application par from file "map.ncd". "vgacam" is an NCD, version 2.28, device xc4010xl, package pc84, speed -3 Loading device for application par from file '4010xl.nph' in environment D:/Xilinx/fndtn. Device speed data version: C 1.1.2.2 FINAL. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 52 out of 61 85% Flops: 31 Latches: 0 Number of CLBs 233 out of 400 58% Total Latches: 0 out of 800 0% Total CLB Flops: 202 out of 800 25% 4 input LUTs: 377 out of 800 47% 3 input LUTs: 89 out of 400 22% Number of BUFGLSs 3 out of 8 37% Number of MODE1s 1 out of 1 100% Overall effort level (-ol): 2 (set by user) Placer effort level (-pl): 2 (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): 2 (set by user) The Placer has detected elements in this design that imply a RAM block structure and will attempt to take advantage of this structure. To disable this behavior, you can set the PAR_NOGENRAMBLOCK environment variable. The Placer builds ram blocks in vertical allignment with respect to "Data In" and "Write Enable" signals. This is the best for this device due to it's routing characteristics. This allignment is not always the best for all designs due to different design methodologies. If you would like the ram blocks generated to be alligned horizontally set the PAR_HORIZONTAL_RAMBLOCK environment variable. Starting initial Placement phase. REAL time: 3 secs Finished initial Placement phase. REAL time: 3 secs Starting Constructive Placer. REAL time: 3 secs Placer score = 148890 Placer score = 118440 Placer score = 108270 Placer score = 104370 Placer score = 95520 Placer score = 91620 Placer score = 87210 Placer score = 86280 Placer score = 83700 Placer score = 82320 Placer score = 78780 Placer score = 77400 Placer score = 74490 Placer score = 72600 Placer score = 70410 Placer score = 69510 Placer score = 68940 Placer score = 67710 Placer score = 66960 Placer score = 65850 Placer score = 65160 Placer score = 64740 Placer score = 64560 Placer score = 63990 Finished Constructive Placer. REAL time: 12 secs Writing design to file "vgacam.ncd". Starting Optimizing Placer. REAL time: 12 secs Optimizing Swapped 3 comps. Xilinx Placer [1] 63750 REAL time: 13 secs Finished Optimizing Placer. REAL time: 13 secs Writing design to file "vgacam.ncd". Total REAL time to Placer completion: 14 secs Total CPU time to Placer completion: 13 secs 0 connection(s) routed; 1938 unrouted active, 1 unrouted PWR/GND. Starting router resource preassignment Completed router resource preassignment. REAL time: 25 secs Starting iterative routing. Routing active signals. End of iteration 1 1938 successful; 0 unrouted active, 1 unrouted PWR/GND; (0) REAL time: 27 secs End of iteration 2 1938 successful; 0 unrouted active, 1 unrouted PWR/GND; (0) REAL time: 27 secs Constraints are met. Routing PWR/GND nets. Power and ground nets completely routed. Writing design to file "vgacam.ncd". Starting cleanup Improving routing. End of cleanup iteration 1 1939 successful; 0 unrouted; (0) REAL time: 32 secs Writing design to file "vgacam.ncd". Total REAL time: 33 secs Total CPU time: 31 secs End of route. 1939 routed (100.00%); 0 unrouted. No errors found. Completely routed. This design was run without timing constraints. It is likely that much better circuit performance can be obtained by trying either or both of the following: - Enabling the Delay Based Cleanup router pass, if not already enabled - Supplying timing constraints in the input design Total REAL time to Router completion: 33 secs Total CPU time to Router completion: 32 secs Generating PAR statistics. Writing design to file "vgacam.ncd". All signals are completely routed. Total REAL time to PAR completion: 34 secs Total CPU time to PAR completion: 33 secs PAR done. ================================================== trce vgacam.ncd vgacam.pcf -e 3 -o vgacam.twr Xilinx TRACE, Version C.21 Copyright (c) 1995-1999 Xilinx, Inc. All rights reserved. Loading device database for application trce from file "vgacam.ncd". "vgacam" is an NCD, version 2.28, device xc4010xl, package pc84, speed -3 Loading device for application trce from file '4010xl.nph' in environment D:/Xilinx/fndtn. -------------------------------------------------------------------------------- Xilinx TRACE, Version C.21 Copyright (c) 1995-1999 Xilinx, Inc. All rights reserved. Design file: vgacam.ncd Physical constraint file: vgacam.pcf Device,speed: xc4010xl,-3 (C 1.1.2.2 FINAL) Report level: error report -------------------------------------------------------------------------------- WARNING:Timing:181 - No timing constraints found, doing default enumeration. Timing summary: --------------- Timing errors: 0 Score: 0 Constraints cover 43796 paths, 444 nets, and 1938 connections (100.0% coverage) Design statistics: Minimum period: 71.827ns (Maximum frequency: 13.922MHz) Maximum net delay: 17.843ns WARNING:Timing:33 - Clock nets using non-dedicated resources were found in this design. Clock skew on these resources will not be automatically addressed during path analysis. To create a timing report that analyzes clock skew for these paths, run trce with the '-skew' option. Analysis completed Mon May 01 16:59:03 2000 -------------------------------------------------------------------------------- Total time: 5 secs ================================================== ngdanno vgacam.ncd map.ngm ngdanno: version C.21 Copyright (c) 1995-1999 Xilinx, Inc. All rights reserved. Loading device database for application ngdanno from file "vgacam.ncd". "vgacam" is an NCD, version 2.28, device xc4010xl, package pc84, speed -3 Loading device for application ngdanno from file '4010xl.nph' in environment D:/Xilinx/fndtn. Reading .ngm file "map.ngm"... Building NGA image... Annotating NGA image... Distributing delays... WARNING:Anno:26 - NGDANNO found physical components for which 100 percent back-annotation is not possible. (These components are listed below.) Some reasons these components may not be fully back-annotatable include: 1. The logic was replicated during physical mapping. 2. MAP was directed to optimize the logic through use of the -oe or -os option, or the OPTIMIZE or OPT_EFFORT design attribute. 3. The component's configuration implies a more complex delay model than can be accurately represented in the original design logic. An example of such a configuration is an XC4000-family CLB containing both carry logic and multiple flip-flops. Simulation models for the following components will be constructed from the NCD netlist. Signal names buried within these components will be lost. COLADDR<1> COLADDR<3> COLADDR<5> H1/H4/RE_CNT2 H1/H4/RE_CNT4 H1/H4/WR_CNT2 H1/H4/WR_CNT4 HCNT<2> HCNT<4> HCNT<6> ROWADDR<1> ROWADDR<3> ROWADDR<5> VCNT<2> VCNT<4> VCNT<6> Writing .nga file "vgacam.nga"... 272 logical models annotated 16 physical models annotated ================================================== ngd2edif -w -v fndtn vgacam.nga time_sim.edn ngd2edif: version C.21 Copyright (c) 1995-1999 Xilinx, Inc. All rights reserved. writing only delay properties to EDIF file dedicated signals will be given global scope running NGD DRC ... writing EDIF file to 'time_sim.edn' ... memory initialization file written to "time_sim.xmm". ================================================== xcpy time_sim.edn D:\CAM\VGACAM\time_sim.edn ================================================== bitgen vgacam.ncd -l -w -f bitgen.ut BITGEN: Xilinx Bitstream Generator C.21 Copyright (c) 1995-1999 Xilinx, Inc. All rights reserved. Loading device database for application Bitgen from file "vgacam.ncd". "vgacam" is an NCD, version 2.28, device xc4010xl, package pc84, speed -3 Loading device for application Bitgen from file '4010xl.nph' in environment D:/Xilinx/fndtn. Opened constraints file vgacam.pcf. Mon May 01 16:59:30 2000 Running DRC. DRC detected 0 errors and 0 warnings. Saving ll file in "vgacam.ll". Creating bit map... Saving bit stream in "vgacam.bit". ================================================== xcpy vgacam.bit D:\CAM\VGACAM\vgacam.bit ================================================== xcpy vgacam.ll D:\CAM\VGACAM\vgacam.ll