// Xilinx TestFixture Template produced by program ngd2ver C.18
// Command: -w -tf vgacam.nga time_sim.v 
// Options: -w -tf -log ngd2ver.log -ti uut 
// Date: Wed Oct 27 14:27:29 1999 
// Input file: vgacam.nga
// Output file: time_sim.v
// Tmp file: C:/TEMP/xil_5
// Design name: vgacam
// Xilinx: G:/Xilinx/fndtn
// # of Modules: 1

// ATTENTION: This file was created by NGD2VER and may therefore be overwritten
// by subsequent runs of NGD2VER. Xilinx recommends that you copy this file to
// a new name, or 'paste' this text into another file, to avoid accidental loss
// of data.

`include "G:\Xilinx\fndtn\verilog\src\glbl.v"
`timescale 1 ns/1 ps

  module test;
    wire \H3/PADRGB7 ;
    wire \H3/PADRGB6 ;
    wire \H3/PADRGB5 ;
    wire \H3/PADRGB4 ;
    wire \H3/PADRGB3 ;
    wire \H3/PADRGB2 ;
    wire \H3/PADRGB1 ;
    wire \H3/PADRGB0 ;
    wire \H3/PADVSYNC ;
    wire \H3/PADHSYNC ;
    wire \H2/PADADDR14 ;
    wire \H2/PADADDR13 ;
    wire \H2/PADADDR12 ;
    wire \H2/PADADDR11 ;
    wire \H2/PADADDR10 ;
    wire \H2/PADADDR9 ;
    wire \H2/PADADDR8 ;
    wire \H2/PADADDR7 ;
    wire \H2/PADADDR6 ;
    wire \H2/PADADDR5 ;
    wire \H2/PADADDR4 ;
    wire \H2/PADADDR3 ;
    wire \H2/PADADDR2 ;
    wire \H2/PADADDR1 ;
    wire \H2/PADADDR0 ;
    wire \H2/PADDATA7 ;
    wire \H2/PADDATA6 ;
    wire \H2/PADDATA5 ;
    wire \H2/PADDATA4 ;
    wire \H2/PADDATA3 ;
    wire \H2/PADDATA2 ;
    wire \H2/PADDATA1 ;
    wire \H2/PADDATA0 ;
    wire \H2/PADOE ;
    wire \H2/PADWR ;
    wire \H2/PADCS ;
    wire \H2/PADADDR15 ;
    wire \H2/PADADDR16 ;
    reg \H1/PAD_CAM3 ;
    reg \H1/PAD_CAM2 ;
    reg \H1/PAD_CAM1 ;
    reg \H1/PAD_CAM0 ;
    reg \H1/PAD_QCK ;
    reg \H1/PAD_FST ;
    reg PC_D0;
    reg PC_D1;
    reg PAD_CLK;
    wire PAR0;
    wire PAR1;
    reg GSR;
    assign glbl.GSR = GSR;
    reg GTS;
    assign glbl.GTS = GTS;

    vgacam uut (
      .\H3/PADRGB7  (\H3/PADRGB7 ),
      .\H3/PADRGB6  (\H3/PADRGB6 ),
      .\H3/PADRGB5  (\H3/PADRGB5 ),
      .\H3/PADRGB4  (\H3/PADRGB4 ),
      .\H3/PADRGB3  (\H3/PADRGB3 ),
      .\H3/PADRGB2  (\H3/PADRGB2 ),
      .\H3/PADRGB1  (\H3/PADRGB1 ),
      .\H3/PADRGB0  (\H3/PADRGB0 ),
      .\H3/PADVSYNC  (\H3/PADVSYNC ),
      .\H3/PADHSYNC  (\H3/PADHSYNC ),
      .\H2/PADADDR14  (\H2/PADADDR14 ),
      .\H2/PADADDR13  (\H2/PADADDR13 ),
      .\H2/PADADDR12  (\H2/PADADDR12 ),
      .\H2/PADADDR11  (\H2/PADADDR11 ),
      .\H2/PADADDR10  (\H2/PADADDR10 ),
      .\H2/PADADDR9  (\H2/PADADDR9 ),
      .\H2/PADADDR8  (\H2/PADADDR8 ),
      .\H2/PADADDR7  (\H2/PADADDR7 ),
      .\H2/PADADDR6  (\H2/PADADDR6 ),
      .\H2/PADADDR5  (\H2/PADADDR5 ),
      .\H2/PADADDR4  (\H2/PADADDR4 ),
      .\H2/PADADDR3  (\H2/PADADDR3 ),
      .\H2/PADADDR2  (\H2/PADADDR2 ),
      .\H2/PADADDR1  (\H2/PADADDR1 ),
      .\H2/PADADDR0  (\H2/PADADDR0 ),
      .\H2/PADDATA7  (\H2/PADDATA7 ),
      .\H2/PADDATA6  (\H2/PADDATA6 ),
      .\H2/PADDATA5  (\H2/PADDATA5 ),
      .\H2/PADDATA4  (\H2/PADDATA4 ),
      .\H2/PADDATA3  (\H2/PADDATA3 ),
      .\H2/PADDATA2  (\H2/PADDATA2 ),
      .\H2/PADDATA1  (\H2/PADDATA1 ),
      .\H2/PADDATA0  (\H2/PADDATA0 ),
      .\H2/PADOE  (\H2/PADOE ),
      .\H2/PADWR  (\H2/PADWR ),
      .\H2/PADCS  (\H2/PADCS ),
      .\H2/PADADDR15  (\H2/PADADDR15 ),
      .\H2/PADADDR16  (\H2/PADADDR16 ),
      .\H1/PAD_CAM3  (\H1/PAD_CAM3 ),
      .\H1/PAD_CAM2  (\H1/PAD_CAM2 ),
      .\H1/PAD_CAM1  (\H1/PAD_CAM1 ),
      .\H1/PAD_CAM0  (\H1/PAD_CAM0 ),
      .\H1/PAD_QCK  (\H1/PAD_QCK ),
      .\H1/PAD_FST  (\H1/PAD_FST ),
      .PC_D0 (PC_D0),
      .PC_D1 (PC_D1),
      .PAD_CLK (PAD_CLK),
      .PAR0 (PAR0),
      .PAR1 (PAR1)
    );
    initial begin
      $timeformat(-9,3,"ns",12);
    end
    initial begin
      $display("           T HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHPPPPP");
      $display("           i 33333333332222222222222222222222222222111111CCAAA");
      $display("           m ////////////////////////////////////////////__DRR");
      $display("           e PPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPDD_01");
      $display("             AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA01C  ");
      $display("             DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD  L  ");
      $display("             RRRRRRRRVHAAAAAAAAAAAAAAADDDDDDDDOWCAA______  K  ");
      $display("             GGGGGGGGSSDDDDDDDDDDDDDDDAAAAAAAAERSDDCCCCQF     ");
      $display("             BBBBBBBBYYDDDDDDDDDDDDDDDTTTTTTTT   DDAAAACS     ");
      $display("             76543210NNRRRRRRRRRRRRRRRAAAAAAAA   RRMMMMKT     ");
      $display("                     CC11111987654321076543210   113210       ");
      $display("                       43210                     56           ");
      $monitor("%t",$realtime,,\H3/PADRGB7 ,\H3/PADRGB6 ,\H3/PADRGB5 ,
      \H3/PADRGB4 ,\H3/PADRGB3 ,\H3/PADRGB2 ,\H3/PADRGB1 ,\H3/PADRGB0 ,\H3/PADVSYNC ,
      \H3/PADHSYNC ,\H2/PADADDR14 ,\H2/PADADDR13 ,\H2/PADADDR12 ,\H2/PADADDR11 ,
      \H2/PADADDR10 ,\H2/PADADDR9 ,\H2/PADADDR8 ,\H2/PADADDR7 ,\H2/PADADDR6 ,
      \H2/PADADDR5 ,\H2/PADADDR4 ,\H2/PADADDR3 ,\H2/PADADDR2 ,\H2/PADADDR1 ,
      \H2/PADADDR0 ,\H2/PADDATA7 ,\H2/PADDATA6 ,\H2/PADDATA5 ,\H2/PADDATA4 ,
      \H2/PADDATA3 ,\H2/PADDATA2 ,\H2/PADDATA1 ,\H2/PADDATA0 ,\H2/PADOE ,\H2/PADWR ,
      \H2/PADCS ,\H2/PADADDR15 ,\H2/PADADDR16 ,\H1/PAD_CAM3 ,\H1/PAD_CAM2 ,
      \H1/PAD_CAM1 ,\H1/PAD_CAM0 ,\H1/PAD_QCK ,\H1/PAD_FST ,PC_D0,PC_D1,PAD_CLK,PAR0,
      PAR1);
    end
    initial begin
        GSR = 1;
        GTS = 0;
      #100
        GSR = 0;
      #1000 $stop;
      // #1000 $finish;
    end
  endmodule