module syncgen (hcnt, vcnt, hsync, vsync) ;

input [9:0] hcnt ;
input [9:1] vcnt ;	// Bit 0 is a don't care, so we have to leave it out
output hsync ;
output vsync ;

// This module defines when the horizontal sync and vertical sync are asserted
// By asserting these syncs in the middle of the blank region, we are in effect
// centering the image displayed on the screen
// The horizontal count goes to 759
// The vertical count goes to 527

// There is a vile bug in the synthesis tools which throws away individual bits in
// busses attached to pins that are not used.  Xilinx says the bug is being fixed
// but for now we have to work around it

assign hsync = !((hcnt>=582)&&(hcnt<=674));	// These are magic numbers!
//assign vsync = !(vcnt>=490)&&(vcnt<=491);
assign vsync = !(vcnt==245);			// A hack to avoid the synthesis bug

endmodule