module MemControl (ReadA, ReadB, WriteB, BusyB, PortSelect, WRITE_L) ;

input ReadA ;		// Port A Read request
input ReadB ;		// Port B Read request
input WriteB ;		// Port B Write request
output BusyB ;		// Port B request is not performed
output PortSelect ;	// Selects Port A or B to perform request
output WRITE_L ;	// Write control to memory

// This module does the arbitration between the two memory ports,
//    an A port, which only supports reads, 
//    and a B port which supports both reads and writes.
// A request is made by asserting Read or Write along with the Address
//    (and Data if it is a Write request).
// The Busy signal is output on the same cycle as the request is made.
// If Busy is not asserted, then the request will be performed.
// Read data is returned on the *next* cycle after the request.
// A new request may be made on every cycle.
// Port A has priority over Port B: i.e. Port A can never be Busy.
// Reading Port B is the default operation even if not requested, so
// it doesn't have to be requested.  (This reduces the hardware at the
//    expense of increased power)

assign BusyB = (ReadA);		// Port A overwrites Port B
assign PortSelect = !BusyB;	// Select PortB if it is not Busy
assign WRITE_L = !(WriteB && !BusyB);  // Write if Port B requests and is not Busy

endmodule