set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector Vector_Name_1 COLADDR8 COLADDR7 COLADDR6 COLADDR5 COLADDR4 COLADDR3 COLADDR2 COLADDR1 COLADDR0 radix hex coladdr | Incorrect signal or pin name: coladdr vector Vector_Name_2 PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 radix hex camin | Incorrect signal or pin name: camin vector Vector_Name_3 ROWADDR8 ROWADDR7 ROWADDR6 ROWADDR5 ROWADDR4 ROWADDR3 ROWADDR2 ROWADDR1 ROWADDR0 radix hex rowaddr | Incorrect signal or pin name: rowaddr vector Vector_Name_4 CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 radix binary camout | Incorrect signal or pin name: camout | Watched Signals and Vectors | | Define your signal and vector watch list here watch CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 watch CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 WRFIFO CAMDATAIN3 watch CAMDATAIN2 CAMDATAIN1 CAMDATAIN0 PAD_CAM3 PAD_CAM2 watch PAD_CAM1 PAD_CAM0 WRITE CLK BUSY READFIFO EMPTY PADFST PADQCK | Incorrect signal or pin name: PADFST | Incorrect signal or pin name: PADQCK assign QCK 0 assign fst 0 assign busy 0 assign camin 0 | Incorrect signal or pin name: camin cycle assign fst 1 cycle assign fst 0 cycle assign camin 5 | Incorrect state value assign QCK 1 cycle 2 assign camin 5 | Incorrect state value assign QCK 0 cycle 2 assign camin 3 | Incorrect state value assign QCK 1 cycle 2 assign camin 3 | Incorrect state value assign QCK 0 cycle 2 assign camin 2 | Incorrect state value assign QCK 1 cycle 2 assign camin 2 | Incorrect state value assign QCK 0 cycle 2 assign camin 1 | Incorrect signal or pin name: camin assign QCK 1 cycle 2 assign camin 1 | Incorrect signal or pin name: camin assign QCK 0 cycle 2 assign camin 5 | Incorrect state value assign QCK 1 cycle 2 assign camin 5 | Incorrect state value assign QCK 0 cycle 2 assign camin 5 | Incorrect state value assign QCK 1 cycle 2 assign camin 5 | Incorrect state value assign QCK 0 cycle 2 sim | End of macro file encountered | The file has been automatically generated by | the Script Editor File Wizard version 2.0.1.89 | | Copyright | Initial settings delete_signals clpr log | Removing existing log file log log | Macro log file Z:\AMMERMAN\CSE567\WORKING\VGACAM\log.log is already opened set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector coladdr COLADDR8 COLADDR7 COLADDR6 COLADDR5 COLADDR4 COLADDR3 COLADDR2 COLADDR1 COLADDR0 radix hex coladdr vector camin PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 radix hex camin vector rowaddr ROWADDR8 ROWADDR7 ROWADDR6 ROWADDR5 ROWADDR4 ROWADDR3 ROWADDR2 ROWADDR1 ROWADDR0 radix hex rowaddr vector camout CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 radix binary camout | Watched Signals and Vectors | | Define your signal and vector watch list here watch CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 watch CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 WRFIFO CAMDATAIN3 watch CAMDATAIN2 CAMDATAIN1 CAMDATAIN0 PAD_CAM3 PAD_CAM2 watch PAD_CAM1 PAD_CAM0 WRITE CLK BUSY READFIFO EMPTY PADFST PADQCK | Incorrect signal or pin name: PADFST | Incorrect signal or pin name: PADQCK assign QCK 0 assign fst 0 assign busy 0 assign camin 0 cycle assign fst 1 cycle assign fst 0 cycle assign camin 5 | Incorrect state value assign QCK 1 cycle 2 assign camin 5 | Incorrect state value assign QCK 0 cycle 2 assign camin 3 | Incorrect state value assign QCK 1 cycle 2 assign camin 3 | Incorrect state value assign QCK 0 cycle 2 assign camin 2 | Incorrect state value assign QCK 1 cycle 2 assign camin 2 | Incorrect state value assign QCK 0 cycle 2 assign camin 1 assign QCK 1 cycle 2 assign camin 1 assign QCK 0 cycle 2 assign camin 5 | Incorrect state value assign QCK 1 cycle 2 assign camin 5 | Incorrect state value assign QCK 0 cycle 2 assign camin 5 | Incorrect state value assign QCK 1 cycle 2 assign camin 5 | Incorrect state value assign QCK 0 cycle 2 sim | End of macro file encountered | The file has been automatically generated by | the Script Editor File Wizard version 2.0.1.89 | | Copyright | Initial settings delete_signals clpr log | Removing existing log file log log | Macro log file Z:\AMMERMAN\CSE567\WORKING\VGACAM\log.log is already opened set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector coladdr COLADDR8 COLADDR7 COLADDR6 COLADDR5 COLADDR4 COLADDR3 COLADDR2 COLADDR1 COLADDR0 radix hex coladdr vector camin PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 radix hex camin vector rowaddr ROWADDR8 ROWADDR7 ROWADDR6 ROWADDR5 ROWADDR4 ROWADDR3 ROWADDR2 ROWADDR1 ROWADDR0 radix hex rowaddr vector camout CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 radix binary camout | Watched Signals and Vectors | | Define your signal and vector watch list here watch CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 watch CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 WRFIFO CAMDATAIN3 watch CAMDATAIN2 CAMDATAIN1 CAMDATAIN0 PAD_CAM3 PAD_CAM2 watch PAD_CAM1 PAD_CAM0 WRITE CLK BUSY READFIFO EMPTY PAD_FST PAD_QCK assign pad_qck 0 assign pad_fst 0 assign busy 0 assign camin 0 cycle assign pad_fst 1 cycle assign pad_fst 0 cycle assign camin 5 | Incorrect state value assign pad_qck 1 cycle 2 assign camin 5 | Incorrect state value assign pad_qck 0 cycle 2 assign camin 3 | Incorrect state value assign QCK 1 cycle 2 assign camin 3 | Incorrect state value assign pad_qck 0 cycle 2 assign camin 2 | Incorrect state value assign pad_qck 1 cycle 2 assign camin 2 | Incorrect state value assign pad_qck 0 cycle 2 assign camin 1 assign pad_qck 1 cycle 2 assign camin 1 assign pad_qck 0 cycle 2 assign camin 5 | Incorrect state value assign pad_qck 1 cycle 2 assign camin 5 | Incorrect state value assign pad_qck 0 cycle 2 assign camin 5 | Incorrect state value assign pad_qck 1 cycle 2 assign camin 5 | Incorrect state value assign pad_qck 0 cycle 2 sim | End of macro file encountered | The file has been automatically generated by | the Script Editor File Wizard version 2.0.1.89 | | Copyright | Initial settings delete_signals clpr log | Removing existing log file log log | Macro log file Z:\AMMERMAN\CSE567\WORKING\VGACAM\log.log is already opened set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector coladdr COLADDR8 COLADDR7 COLADDR6 COLADDR5 COLADDR4 COLADDR3 COLADDR2 COLADDR1 COLADDR0 radix hex coladdr vector camin PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 radix hex camin vector rowaddr ROWADDR8 ROWADDR7 ROWADDR6 ROWADDR5 ROWADDR4 ROWADDR3 ROWADDR2 ROWADDR1 ROWADDR0 radix hex rowaddr vector camout CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 radix binary camout | Watched Signals and Vectors | | Define your signal and vector watch list here watch CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 watch CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 WRFIFO CAMDATAIN3 watch CAMDATAIN2 CAMDATAIN1 CAMDATAIN0 watch camin WRITE CLK BUSY READFIFO EMPTY PAD_FST PAD_QCK assign pad_qck 0 assign pad_fst 0 assign busy 0 assign camin 0 cycle assign pad_fst 1 cycle assign pad_fst 0 cycle assign camin 5 | Incorrect state value assign pad_qck 1 cycle 2 assign camin 5 | Incorrect state value assign pad_qck 0 cycle 2 assign camin 3 | Incorrect state value assign QCK 1 cycle 2 assign camin 3 | Incorrect state value assign pad_qck 0 cycle 2 assign camin 2 | Incorrect state value assign pad_qck 1 cycle 2 assign camin 2 | Incorrect state value assign pad_qck 0 cycle 2 assign camin 1 assign pad_qck 1 cycle 2 assign camin 1 assign pad_qck 0 cycle 2 assign camin 5 | Incorrect state value assign pad_qck 1 cycle 2 assign camin 5 | Incorrect state value assign pad_qck 0 cycle 2 assign camin 5 | Incorrect state value assign pad_qck 1 cycle 2 assign camin 5 | Incorrect state value assign pad_qck 0 cycle 2 sim | End of macro file encountered | The file has been automatically generated by | the Script Editor File Wizard version 2.0.1.89 | | Copyright | Initial settings delete_signals clpr log | Removing existing log file log log | Macro log file Z:\AMMERMAN\CSE567\WORKING\VGACAM\log.log is already opened set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector coladdr COLADDR8 COLADDR7 COLADDR6 COLADDR5 COLADDR4 COLADDR3 COLADDR2 COLADDR1 COLADDR0 radix hex coladdr |vector camin PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 |radix hex camin vector rowaddr ROWADDR8 ROWADDR7 ROWADDR6 ROWADDR5 ROWADDR4 ROWADDR3 ROWADDR2 ROWADDR1 ROWADDR0 radix hex rowaddr vector camout CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 radix binary camout | Watched Signals and Vectors | | Define your signal and vector watch list here watch CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 watch CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 WRFIFO CAMDATAIN3 watch CAMDATAIN2 CAMDATAIN1 CAMDATAIN0 PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 watch camin WRITE CLK BUSY READFIFO EMPTY PAD_FST PAD_QCK | Incorrect signal or pin name: camin assign pad_qck 0 assign pad_fst 0 assign busy 0 |assign camin 0 assign PAD_CAM3 1 assign PAD_CAM2 1 assign PAD_CAM1 1 assign PAD_CAM0 1 cycle assign pad_fst 1 cycle assign pad_fst 0 cycle assign PAD_CAM3 1 assign PAD_CAM2 0 assign PAD_CAM1 1 assign PAD_CAM0 0 assign pad_qck 1 cycle 2 assign camin 5 | Incorrect state value assign pad_qck 0 cycle 2 assign camin 3 | Incorrect state value assign QCK 1 cycle 2 assign camin 3 | Incorrect state value assign pad_qck 0 cycle 2 assign camin 2 | Incorrect state value assign pad_qck 1 cycle 2 assign camin 2 | Incorrect state value assign pad_qck 0 cycle 2 assign camin 1 | Incorrect signal or pin name: camin assign pad_qck 1 cycle 2 assign camin 1 | Incorrect signal or pin name: camin assign pad_qck 0 cycle 2 assign camin 5 | Incorrect state value assign pad_qck 1 cycle 2 assign camin 5 | Incorrect state value assign pad_qck 0 cycle 2 assign camin 5 | Incorrect state value assign pad_qck 1 cycle 2 assign camin 5 | Incorrect state value assign pad_qck 0 cycle 2 sim | End of macro file encountered | The file has been automatically generated by | the Script Editor File Wizard version 2.0.1.89 | | Copyright | Initial settings delete_signals clpr log | Removing existing log file log log | Macro log file Z:\AMMERMAN\CSE567\WORKING\VGACAM\log.log is already opened set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector coladdr COLADDR8 COLADDR7 COLADDR6 COLADDR5 COLADDR4 COLADDR3 COLADDR2 COLADDR1 COLADDR0 radix hex coladdr |vector camin PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 |radix hex camin vector rowaddr ROWADDR8 ROWADDR7 ROWADDR6 ROWADDR5 ROWADDR4 ROWADDR3 ROWADDR2 ROWADDR1 ROWADDR0 radix hex rowaddr vector camout CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 radix binary camout | Watched Signals and Vectors | | Define your signal and vector watch list here watch CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 watch CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 WRFIFO CAMDATAIN3 watch CAMDATAIN2 CAMDATAIN1 CAMDATAIN0 PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 watch camin WRITE CLK BUSY READFIFO EMPTY PAD_FST PAD_QCK | Incorrect signal or pin name: camin assign pad_qck 0 assign pad_fst 0 assign busy 0 |assign camin 0 assign PAD_CAM3 1 assign PAD_CAM2 1 assign PAD_CAM1 1 assign PAD_CAM0 1 cycle assign pad_fst 1 cycle assign pad_fst 0 cycle assign PAD_CAM3 1 assign PAD_CAM2 0 assign PAD_CAM1 1 assign PAD_CAM0 0 assign pad_qck 1 cycle 2 assign camin 5 | Incorrect state value assign pad_qck 0 cycle 2 assign camin 3 | Incorrect state value assign QCK 1 cycle 2 assign camin 3 | Incorrect state value assign pad_qck 0 cycle 2 assign camin 2 | Incorrect state value assign pad_qck 1 cycle 2 assign camin 2 | Incorrect state value assign pad_qck 0 cycle 2 assign camin 1 | Incorrect signal or pin name: camin assign pad_qck 1 cycle 2 assign camin 1 | Incorrect signal or pin name: camin assign pad_qck 0 cycle 2 assign camin 5 | Incorrect state value assign pad_qck 1 cycle 2 assign camin 5 | Incorrect state value assign pad_qck 0 cycle 2 assign camin 5 | Incorrect state value assign pad_qck 1 cycle 2 assign camin 5 | Incorrect state value assign pad_qck 0 cycle 2 sim | End of macro file encountered | The file has been automatically generated by | the Script Editor File Wizard version 2.0.1.89 | | Copyright | Initial settings delete_signals clpr log | Removing existing log file log log | Macro log file Z:\AMMERMAN\CSE567\WORKING\VGACAM\log.log is already opened set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector coladdr COLADDR8 COLADDR7 COLADDR6 COLADDR5 COLADDR4 COLADDR3 COLADDR2 COLADDR1 COLADDR0 radix hex coladdr vector camin PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 radix hex camin vector rowaddr ROWADDR8 ROWADDR7 ROWADDR6 ROWADDR5 ROWADDR4 ROWADDR3 ROWADDR2 ROWADDR1 ROWADDR0 radix hex rowaddr vector camout CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 radix binary camout | Watched Signals and Vectors | | Define your signal and vector watch list here watch CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 watch CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 WRFIFO CAMDATAIN3 watch CAMDATAIN2 CAMDATAIN1 CAMDATAIN0 PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 watch camin WRITE CLK BUSY READFIFO EMPTY PAD_FST PAD_QCK assign pad_qck 0 assign pad_fst 0 assign busy 0 assign camin 0\h cycle assign pad_fst 1 cycle assign pad_fst 0 cycle assign camin 5\h assign pad_qck 1 cycle 2 assign camin 5\h assign pad_qck 0 cycle 2 assign camin 3\h assign QCK 1 cycle 2 assign camin 3\h assign pad_qck 0 cycle 2 assign camin 2\h assign pad_qck 1 cycle 2 assign camin 2\h assign pad_qck 0 cycle 2 assign camin 1\h assign pad_qck 1 cycle 2 assign camin 1\h assign pad_qck 0 cycle 2 assign camin 5\h assign pad_qck 1 cycle 2 assign camin 5\h assign pad_qck 0 cycle 2 assign camin 5 | Incorrect state value assign pad_qck 1 cycle 2 assign camin 5 | Incorrect state value assign pad_qck 0 cycle 2 sim | End of macro file encountered | The file has been automatically generated by | the Script Editor File Wizard version 2.0.1.89 | | Copyright | Initial settings delete_signals clpr log | Removing existing log file log log | Macro log file Z:\AMMERMAN\CSE567\WORKING\VGACAM\log.log is already opened set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector coladdr COLADDR8 COLADDR7 COLADDR6 COLADDR5 COLADDR4 COLADDR3 COLADDR2 COLADDR1 COLADDR0 radix hex coladdr vector camin PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 radix hex camin vector rowaddr ROWADDR8 ROWADDR7 ROWADDR6 ROWADDR5 ROWADDR4 ROWADDR3 ROWADDR2 ROWADDR1 ROWADDR0 radix hex rowaddr vector camout CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 radix binary camout | Watched Signals and Vectors | | Define your signal and vector watch list here watch rowaddr camout coladdr watch camin WRITE CLK BUSY READFIFO EMPTY PAD_FST PAD_QCK assign pad_qck 0 assign pad_fst 0 assign busy 0 assign camin 0\h cycle assign pad_fst 1 cycle assign pad_fst 0 cycle assign camin 5\h assign pad_qck 1 cycle 2 assign camin 5\h assign pad_qck 0 cycle 2 assign camin 3\h assign QCK 1 cycle 2 assign camin 3\h assign pad_qck 0 cycle 2 assign camin 2\h assign pad_qck 1 cycle 2 assign camin 2\h assign pad_qck 0 cycle 2 assign camin 1\h assign pad_qck 1 cycle 2 assign camin 1\h assign pad_qck 0 cycle 2 assign camin 5\h assign pad_qck 1 cycle 2 assign camin 5\h assign pad_qck 0 cycle 2 assign camin 5\h assign pad_qck 1 cycle 2 assign camin 5\h assign pad_qck 0 cycle 2 sim | End of macro file encountered | The file has been automatically generated by | the Script Editor File Wizard version 2.0.1.89 | | Copyright | Initial settings delete_signals clpr log | Removing existing log file log log | Macro log file Z:\AMMERMAN\CSE567\WORKING\VGACAM\log.log is already opened set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector coladdr COLADDR8 COLADDR7 COLADDR6 COLADDR5 COLADDR4 COLADDR3 COLADDR2 COLADDR1 COLADDR0 radix hex coladdr vector camin PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 radix hex camin vector rowaddr ROWADDR8 ROWADDR7 ROWADDR6 ROWADDR5 ROWADDR4 ROWADDR3 ROWADDR2 ROWADDR1 ROWADDR0 radix hex rowaddr vector camout CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 radix hex camout | Watched Signals and Vectors | | Define your signal and vector watch list here watch rowaddr camout coladdr watch camin WRITE CLK BUSY READFIFO EMPTY PAD_FST PAD_QCK WRITEFIFO | Incorrect signal or pin name: WRITEFIFO assign pad_qck 0 assign pad_fst 0 assign busy 0 assign camin 0\h cycle assign pad_fst 1 cycle assign pad_fst 0 cycle assign camin 5\h assign pad_qck 1 cycle 2 assign camin 5\h assign pad_qck 0 cycle 2 assign camin 3\h assign QCK 1 cycle 2 assign camin 3\h assign pad_qck 0 cycle 2 assign camin 2\h assign pad_qck 1 cycle 2 assign camin 2\h assign pad_qck 0 cycle 2 assign camin 1\h assign pad_qck 1 cycle 2 assign camin 1\h assign pad_qck 0 cycle 2 assign camin 5\h assign pad_qck 1 cycle 2 assign camin 5\h assign pad_qck 0 cycle 2 assign camin 5\h assign pad_qck 1 cycle 2 assign camin 5\h assign pad_qck 0 cycle 2 sim | End of macro file encountered | The file has been automatically generated by | the Script Editor File Wizard version 2.0.1.89 | | Copyright | Initial settings delete_signals clpr log | Removing existing log file log log | Macro log file Z:\AMMERMAN\CSE567\WORKING\VGACAM\log.log is already opened set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector coladdr COLADDR8 COLADDR7 COLADDR6 COLADDR5 COLADDR4 COLADDR3 COLADDR2 COLADDR1 COLADDR0 radix hex coladdr vector camin PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 radix hex camin vector rowaddr ROWADDR8 ROWADDR7 ROWADDR6 ROWADDR5 ROWADDR4 ROWADDR3 ROWADDR2 ROWADDR1 ROWADDR0 radix hex rowaddr vector camout CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 radix hex camout | Watched Signals and Vectors | | Define your signal and vector watch list here watch rowaddr camout coladdr watch camin WRITE CLK BUSY READFIFO EMPTY PAD_FST PAD_QCK WRFIFO assign pad_qck 0 assign pad_fst 0 assign busy 0 assign camin 0\h cycle assign pad_fst 1 cycle assign pad_fst 0 cycle assign camin 5\h assign pad_qck 1 cycle 2 assign camin 5\h assign pad_qck 0 cycle 2 assign camin 3\h assign QCK 1 cycle 2 assign camin 3\h assign pad_qck 0 cycle 2 assign camin 2\h assign pad_qck 1 cycle 2 assign camin 2\h assign pad_qck 0 cycle 2 assign camin 1\h assign pad_qck 1 cycle 2 assign camin 1\h assign pad_qck 0 cycle 2 assign camin 5\h assign pad_qck 1 cycle 2 assign camin 5\h assign pad_qck 0 cycle 2 assign camin 5\h assign pad_qck 1 cycle 2 assign camin 5\h assign pad_qck 0 cycle 2 sim | End of macro file encountered | The file has been automatically generated by | the Script Editor File Wizard version 2.0.1.89 | | Copyright | Initial settings delete_signals clpr log | Removing existing log file log log | Macro log file Z:\AMMERMAN\CSE567\WORKING\VGACAM\log.log is already opened set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector coladdr COLADDR8 COLADDR7 COLADDR6 COLADDR5 COLADDR4 COLADDR3 COLADDR2 COLADDR1 COLADDR0 radix hex coladdr vector camin PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 radix hex camin vector rowaddr ROWADDR8 ROWADDR7 ROWADDR6 ROWADDR5 ROWADDR4 ROWADDR3 ROWADDR2 ROWADDR1 ROWADDR0 radix hex rowaddr vector camout CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 radix hex camout | Watched Signals and Vectors | | Define your signal and vector watch list here watch rowaddr camout coladdr watch camin WRITE CLK BUSY READFIFO EMPTY PAD_FST PAD_QCK WRFIFO assign pad_qck 0 assign pad_fst 0 assign busy 0 assign camin 0\h cycle assign pad_fst 1 cycle 4 assign pad_fst 0 cycle 4 assign camin 5\h assign pad_qck 1 cycle 3 assign camin 5\h assign pad_qck 0 cycle 3 assign camin 3\h assign QCK 1 cycle 3 assign camin 3\h assign pad_qck 0 cycle 3 assign camin 2\h assign pad_qck 1 cycle 3 assign camin 2\h assign pad_qck 0 cycle 3 assign camin 1\h assign pad_qck 1 cycle 3 assign camin 1\h assign pad_qck 0 cycle 3 assign camin 5\h assign pad_qck 1 cycle 3 assign camin 5\h assign pad_qck 0 cycle 3 assign camin 5\h assign pad_qck 1 cycle 3 assign camin 5\h assign pad_qck 0 cycle 3 sim | End of macro file encountered | The file has been automatically generated by | the Script Editor File Wizard version 2.0.1.89 | | Copyright | Initial settings delete_signals clpr log | Removing existing log file log log | Macro log file Z:\AMMERMAN\CSE567\WORKING\VGACAM\log.log is already opened set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector coladdr COLADDR8 COLADDR7 COLADDR6 COLADDR5 COLADDR4 COLADDR3 COLADDR2 COLADDR1 COLADDR0 radix hex coladdr vector camin PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 radix hex camin vector rowaddr ROWADDR8 ROWADDR7 ROWADDR6 ROWADDR5 ROWADDR4 ROWADDR3 ROWADDR2 ROWADDR1 ROWADDR0 radix hex rowaddr vector camout CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 radix hex camout | Watched Signals and Vectors | | Define your signal and vector watch list here watch rowaddr camout coladdr watch camin WRITE CLK BUSY READFIFO EMPTY PAD_FST PAD_QCK WRFIFO assign pad_qck 0 assign pad_fst 0 assign busy 0 assign camin 0\h cycle assign pad_fst 1 cycle 4 assign pad_fst 0 cycle 4 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 5\h cycle 1 assign pad_qck 0 cycle 3 assign camin 3\h cycle 1 assign QCK 1 cycle 3 assign camin 3\h cycle 1 assign pad_qck 0 cycle 3 assign camin 2\h cycle 1 assign pad_qck 1 cycle 3 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 1\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 5\h assign pad_qck 0 cycle 3 assign camin 5\h assign pad_qck 1 cycle 3 assign camin 5\h assign pad_qck 0 cycle 3 sim | End of macro file encountered set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector coladdr COLADDR8 COLADDR7 COLADDR6 COLADDR5 COLADDR4 COLADDR3 COLADDR2 COLADDR1 COLADDR0 radix hex coladdr vector camin PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 radix hex camin vector rowaddr ROWADDR8 ROWADDR7 ROWADDR6 ROWADDR5 ROWADDR4 ROWADDR3 ROWADDR2 ROWADDR1 ROWADDR0 radix hex rowaddr vector camout CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 radix hex camout | Watched Signals and Vectors | | Define your signal and vector watch list here watch rowaddr camout coladdr old_qck new_qck watch camin WRITE CLK BUSY READFIFO EMPTY PAD_FST PAD_QCK WRFIFO assign pad_qck 0 assign pad_fst 0 assign busy 0 assign camin 0\h cycle assign pad_fst 1 cycle 4 assign pad_fst 0 cycle 4 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 5\h cycle 1 assign pad_qck 0 cycle 3 assign camin 3\h cycle 1 assign QCK 1 cycle 3 assign camin 3\h cycle 1 assign pad_qck 0 cycle 3 assign camin 2\h cycle 1 assign pad_qck 1 cycle 3 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 1\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 5\h assign pad_qck 0 cycle 3 assign camin 5\h assign pad_qck 1 cycle 3 assign camin 5\h assign pad_qck 0 cycle 3 sim | End of macro file encountered | The file has been automatically generated by | the Script Editor File Wizard version 2.0.1.89 | | Copyright | Initial settings delete_signals clpr log | Removing existing log file log log | Macro log file Z:\AMMERMAN\CSE567\WORKING\VGACAM\log.log is already opened set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector coladdr COLADDR8 COLADDR7 COLADDR6 COLADDR5 COLADDR4 COLADDR3 COLADDR2 COLADDR1 COLADDR0 radix hex coladdr vector camin PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 radix hex camin vector rowaddr ROWADDR8 ROWADDR7 ROWADDR6 ROWADDR5 ROWADDR4 ROWADDR3 ROWADDR2 ROWADDR1 ROWADDR0 radix hex rowaddr vector camout CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 radix hex camout | Watched Signals and Vectors | | Define your signal and vector watch list here watch rowaddr camout coladdr old_qck new_qck qck watch camin WRITE CLK BUSY READFIFO EMPTY PAD_FST PAD_QCK WRFIFO assign pad_qck 0 assign pad_fst 0 assign busy 0 assign camin 0\h cycle assign pad_fst 1 cycle 4 assign pad_fst 0 cycle 4 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 5\h cycle 1 assign pad_qck 0 cycle 3 assign camin 3\h cycle 1 assign QCK 1 cycle 3 assign camin 3\h cycle 1 assign pad_qck 0 cycle 3 assign camin 2\h cycle 1 assign pad_qck 1 cycle 3 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 1\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 5\h assign pad_qck 0 cycle 3 assign camin 5\h assign pad_qck 1 cycle 3 assign camin 5\h assign pad_qck 0 cycle 3 sim | End of macro file encountered | The file has been automatically generated by | the Script Editor File Wizard version 2.0.1.89 | | Copyright | Initial settings delete_signals clpr log | Removing existing log file log log | Macro log file Z:\AMMERMAN\CSE567\WORKING\VGACAM\log.log is already opened set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector coladdr COLADDR8 COLADDR7 COLADDR6 COLADDR5 COLADDR4 COLADDR3 COLADDR2 COLADDR1 COLADDR0 radix hex coladdr vector camin PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 radix hex camin vector rowaddr ROWADDR8 ROWADDR7 ROWADDR6 ROWADDR5 ROWADDR4 ROWADDR3 ROWADDR2 ROWADDR1 ROWADDR0 radix hex rowaddr vector camout CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 radix hex camout | Watched Signals and Vectors | | Define your signal and vector watch list here watch rowaddr camout coladdr old_qck new_qck qck watch camin WRITE CLK BUSY READFIFO EMPTY PAD_FST PAD_QCK WRFIFO assign pad_qck 0 assign pad_fst 0 assign busy 0 assign camin 0\h cycle assign pad_fst 1 cycle 4 assign pad_fst 0 cycle 4 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 5\h cycle 1 assign pad_qck 0 cycle 3 assign camin 3\h cycle 1 assign QCK 1 cycle 3 assign camin 3\h cycle 1 assign pad_qck 0 cycle 3 assign camin 2\h cycle 1 assign pad_qck 1 cycle 3 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 1\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 5\h assign pad_qck 0 cycle 3 assign camin 5\h assign pad_qck 1 cycle 3 assign camin 5\h assign pad_qck 0 cycle 3 sim | End of macro file encountered set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector coladdr COLADDR8 COLADDR7 COLADDR6 COLADDR5 COLADDR4 COLADDR3 COLADDR2 COLADDR1 COLADDR0 radix hex coladdr vector camin PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 radix hex camin vector rowaddr ROWADDR8 ROWADDR7 ROWADDR6 ROWADDR5 ROWADDR4 ROWADDR3 ROWADDR2 ROWADDR1 ROWADDR0 radix hex rowaddr vector camout CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 radix hex camout | Watched Signals and Vectors | | Define your signal and vector watch list here watch rowaddr camout coladdr old_qck new_qck qck watch camin WRITE CLK BUSY READFIFO EMPTY PAD_FST PAD_QCK WRFIFO assign pad_qck 0 assign pad_fst 0 assign busy 0 assign camin 0\h cycle assign pad_fst 1 cycle 4 assign pad_fst 0 cycle 4 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 5\h cycle 1 assign pad_qck 0 cycle 3 assign camin 3\h cycle 1 assign QCK 1 cycle 3 assign camin 3\h cycle 1 assign pad_qck 0 cycle 3 assign camin 2\h cycle 1 assign pad_qck 1 cycle 3 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 1\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 5\h assign pad_qck 0 cycle 3 assign camin 5\h assign pad_qck 1 cycle 3 assign camin 5\h assign pad_qck 0 cycle 3 sim | End of macro file encountered | The file has been automatically generated by | the Script Editor File Wizard version 2.0.1.89 | | Copyright | Initial settings delete_signals clpr log | Removing existing log file log log | Macro log file Z:\AMMERMAN\CSE567\WORKING\VGACAM\log.log is already opened set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector coladdr COLADDR8 COLADDR7 COLADDR6 COLADDR5 COLADDR4 COLADDR3 COLADDR2 COLADDR1 COLADDR0 radix hex coladdr vector camin PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 radix hex camin vector rowaddr ROWADDR8 ROWADDR7 ROWADDR6 ROWADDR5 ROWADDR4 ROWADDR3 ROWADDR2 ROWADDR1 ROWADDR0 radix hex rowaddr vector camout CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 radix hex camout | Watched Signals and Vectors | | Define your signal and vector watch list here watch rowaddr camout coladdr old_qck new_qck qck watch camin WRITE CLK BUSY READFIFO EMPTY PAD_FST PAD_QCK WRFIFO assign pad_qck 0 assign pad_fst 0 assign busy 0 assign camin 0\h cycle assign pad_fst 1 cycle 4 assign pad_fst 0 cycle 4 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 5\h cycle 1 assign pad_qck 0 cycle 3 assign camin 3\h cycle 1 assign pad_qck 1 cycle 3 assign camin 3\h cycle 1 assign pad_qck 0 cycle 3 assign camin 2\h cycle 1 assign pad_qck 1 cycle 3 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 1\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 5\h assign pad_qck 0 cycle 3 assign camin 5\h assign pad_qck 1 cycle 3 assign camin 5\h assign pad_qck 0 cycle 3 sim | End of macro file encountered set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector coladdr COLADDR8 COLADDR7 COLADDR6 COLADDR5 COLADDR4 COLADDR3 COLADDR2 COLADDR1 COLADDR0 radix hex coladdr vector camin PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 radix hex camin vector rowaddr ROWADDR8 ROWADDR7 ROWADDR6 ROWADDR5 ROWADDR4 ROWADDR3 ROWADDR2 ROWADDR1 ROWADDR0 radix hex rowaddr vector camout CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 radix hex camout | Watched Signals and Vectors | | Define your signal and vector watch list here watch rowaddr camout coladdr watch camin WRITE CLK BUSY READFIFO EMPTY PAD_FST PAD_QCK WRFIFO assign pad_qck 0 assign pad_fst 0 assign busy 0 assign camin 0\h cycle assign pad_fst 1 cycle 4 assign pad_fst 0 cycle 4 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 5\h cycle 1 assign pad_qck 0 cycle 3 assign camin 3\h cycle 1 assign pad_qck 1 cycle 3 assign camin 3\h cycle 1 assign pad_qck 0 cycle 3 assign camin 2\h cycle 1 assign pad_qck 1 cycle 3 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 1\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 5\h assign pad_qck 0 cycle 3 assign camin 5\h assign pad_qck 1 cycle 3 assign camin 5\h assign pad_qck 0 cycle 3 sim | End of macro file encountered | The file has been automatically generated by | the Script Editor File Wizard version 2.0.1.89 | | Copyright | Initial settings delete_signals clpr log | Removing existing log file log log | Macro log file Z:\AMMERMAN\CSE567\WORKING\VGACAM\log.log is already opened set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector coladdr COLADDR8 COLADDR7 COLADDR6 COLADDR5 COLADDR4 COLADDR3 COLADDR2 COLADDR1 COLADDR0 radix hex coladdr vector camin PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 radix hex camin vector rowaddr ROWADDR8 ROWADDR7 ROWADDR6 ROWADDR5 ROWADDR4 ROWADDR3 ROWADDR2 ROWADDR1 ROWADDR0 radix hex rowaddr vector camout CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 radix hex camout | Watched Signals and Vectors | | Define your signal and vector watch list here watch rowaddr camout coladdr watch camin WRITE CLK BUSY READFIFO EMPTY PAD_FST PAD_QCK WRFIFO assign pad_qck 0 assign pad_fst 0 assign busy 0 assign camin 0\h cycle assign pad_fst 1 cycle 4 assign pad_fst 0 cycle 4 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 3\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 2\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 1\h cycle 1 assign pad_qck 1 cycle 3 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 6\h assign pad_qck 0 cycle 3 assign camin 5\h assign pad_qck 1 cycle 3 assign camin 5\h assign pad_qck 0 cycle 3 sim | End of macro file encountered | The file has been automatically generated by | the Script Editor File Wizard version 2.0.1.89 | | Copyright | Initial settings delete_signals clpr log | Removing existing log file log log | Macro log file Z:\AMMERMAN\CSE567\WORKING\VGACAM\log.log is already opened set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector coladdr COLADDR8 COLADDR7 COLADDR6 COLADDR5 COLADDR4 COLADDR3 COLADDR2 COLADDR1 COLADDR0 radix hex coladdr vector camin PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 radix hex camin vector rowaddr ROWADDR8 ROWADDR7 ROWADDR6 ROWADDR5 ROWADDR4 ROWADDR3 ROWADDR2 ROWADDR1 ROWADDR0 radix hex rowaddr vector camout CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 radix hex camout | Watched Signals and Vectors | | Define your signal and vector watch list here watch rowaddr camout coladdr watch camin WRITE CLK BUSY READFIFO EMPTY PAD_FST PAD_QCK WRFIFO assign pad_qck 0 assign pad_fst 0 assign busy 0 assign camin 0\h cycle assign pad_fst 1 cycle 4 assign pad_fst 0 cycle 4 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 3\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 2\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 1\h cycle 1 assign pad_qck 1 cycle 3 assign busy 1 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 6\h assign pad_qck 0 cycle 3 assign camin 5\h assign pad_qck 1 cycle 3 assign camin 5\h assign pad_qck 0 cycle 3 sim | End of macro file encountered | The file has been automatically generated by | the Script Editor File Wizard version 2.0.1.89 | | Copyright | Initial settings delete_signals clpr log | Removing existing log file log log | Macro log file Z:\AMMERMAN\CSE567\WORKING\VGACAM\log.log is already opened set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector coladdr COLADDR8 COLADDR7 COLADDR6 COLADDR5 COLADDR4 COLADDR3 COLADDR2 COLADDR1 COLADDR0 radix hex coladdr vector camin PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 radix hex camin vector rowaddr ROWADDR8 ROWADDR7 ROWADDR6 ROWADDR5 ROWADDR4 ROWADDR3 ROWADDR2 ROWADDR1 ROWADDR0 radix hex rowaddr vector camout CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 radix hex camout | Watched Signals and Vectors | | Define your signal and vector watch list here watch rowaddr camout coladdr watch camin WRITE CLK BUSY READFIFO EMPTY PAD_FST PAD_QCK WRFIFO assign pad_qck 0 assign pad_fst 0 assign busy 0 assign camin 0\h cycle assign pad_fst 1 cycle 4 assign pad_fst 0 cycle 4 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 3\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 2\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 1\h cycle 1 assign pad_qck 1 assign busy 1 cycle 3 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 6\h assign pad_qck 0 cycle 3 assign camin 5\h assign pad_qck 1 cycle 3 assign camin 5\h assign pad_qck 0 cycle 3 sim | End of macro file encountered | The file has been automatically generated by | the Script Editor File Wizard version 2.0.1.89 | | Copyright | Initial settings delete_signals clpr log | Removing existing log file log log | Macro log file Z:\AMMERMAN\CSE567\WORKING\VGACAM\log.log is already opened set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector coladdr COLADDR8 COLADDR7 COLADDR6 COLADDR5 COLADDR4 COLADDR3 COLADDR2 COLADDR1 COLADDR0 radix hex coladdr vector camin PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 radix hex camin vector rowaddr ROWADDR8 ROWADDR7 ROWADDR6 ROWADDR5 ROWADDR4 ROWADDR3 ROWADDR2 ROWADDR1 ROWADDR0 radix hex rowaddr vector camout CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 radix hex camout | Watched Signals and Vectors | | Define your signal and vector watch list here watch rowaddr camout coladdr watch camin WRITE CLK BUSY READFIFO EMPTY PAD_FST PAD_QCK WRFIFO assign pad_qck 0 assign pad_fst 0 assign busy 0 assign camin 0\h cycle assign pad_fst 1 cycle 4 assign pad_fst 0 cycle 4 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 3\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 2\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 1\h cycle 1 assign pad_qck 1 assign busy 1 cycle 3 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 6\h assign pad_qck 0 cycle 3 assign camin 5\h assign pad_qck 1 cycle 3 assign busy 0 assign camin 5\h assign pad_qck 0 cycle 3 sim | End of macro file encountered | The file has been automatically generated by | the Script Editor File Wizard version 2.0.1.89 | | Copyright | Initial settings delete_signals clpr log | Removing existing log file log log | Macro log file Z:\AMMERMAN\CSE567\WORKING\VGACAM\log.log is already opened set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector coladdr COLADDR8 COLADDR7 COLADDR6 COLADDR5 COLADDR4 COLADDR3 COLADDR2 COLADDR1 COLADDR0 radix hex coladdr vector camin PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 radix hex camin vector rowaddr ROWADDR8 ROWADDR7 ROWADDR6 ROWADDR5 ROWADDR4 ROWADDR3 ROWADDR2 ROWADDR1 ROWADDR0 radix hex rowaddr vector camout CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 radix hex camout | Watched Signals and Vectors | | Define your signal and vector watch list here watch rowaddr camout coladdr watch camin WRITE CLK BUSY READFIFO EMPTY PAD_FST PAD_QCK WRFIFO assign pad_qck 0 assign pad_fst 0 assign busy 0 assign camin 0\h cycle assign pad_fst 1 cycle 4 assign pad_fst 0 cycle 4 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 3\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 2\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 1\h cycle 1 assign pad_qck 1 assign busy 1 cycle 3 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 6\h assign pad_qck 0 cycle 3 assign camin 5\h assign pad_qck 1 cycle 3 assign busy 0 assign camin 5\h assign pad_qck 0 cycle 30 sim | End of macro file encountered set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector coladdr COLADDR8 COLADDR7 COLADDR6 COLADDR5 COLADDR4 COLADDR3 COLADDR2 COLADDR1 COLADDR0 radix hex coladdr vector camin PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 radix hex camin vector rowaddr ROWADDR8 ROWADDR7 ROWADDR6 ROWADDR5 ROWADDR4 ROWADDR3 ROWADDR2 ROWADDR1 ROWADDR0 radix hex rowaddr vector camout CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 radix hex camout | Watched Signals and Vectors | | Define your signal and vector watch list here watch rowaddr camout coladdr watch camin WRITE CLK BUSY READFIFO EMPTY PAD_FST PAD_QCK WRFIFO assign pad_qck 0 assign pad_fst 0 assign busy 0 assign camin 0\h cycle assign pad_fst 1 cycle 4 assign pad_fst 0 cycle 4 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 3\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 2\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 1\h cycle 1 assign pad_qck 1 assign busy 1 cycle 3 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 6\h assign pad_qck 0 cycle 3 assign camin 5\h assign pad_qck 1 cycle 3 assign busy 0 assign camin 5\h assign pad_qck 0 cycle 30 sim | End of macro file encountered | The file has been automatically generated by | the Script Editor File Wizard version 2.0.1.89 | | Copyright | Initial settings delete_signals clpr log | Removing existing log file log log | Macro log file Z:\AMMERMAN\CSE567\WORKING\VGACAM\log.log is already opened set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector coladdr COLADDR8 COLADDR7 COLADDR6 COLADDR5 COLADDR4 COLADDR3 COLADDR2 COLADDR1 COLADDR0 radix hex coladdr vector camin PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 radix hex camin vector rowaddr ROWADDR8 ROWADDR7 ROWADDR6 ROWADDR5 ROWADDR4 ROWADDR3 ROWADDR2 ROWADDR1 ROWADDR0 radix hex rowaddr vector camout CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 radix hex camout | Watched Signals and Vectors | | Define your signal and vector watch list here watch rowaddr camout coladdr watch camin WRITE CLK BUSY READFIFO EMPTY PAD_FST PAD_QCK WRFIFO assign pad_qck 0 assign pad_fst 0 assign busy 0 assign camin 0\h cycle assign pad_fst 1 cycle 4 assign pad_fst 0 cycle 4 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 3\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 2\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 1\h cycle 1 assign pad_qck 1 |assign busy 1 cycle 1 assign busy 1 cycle 2 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 6\h assign pad_qck 0 cycle 3 assign camin 5\h assign pad_qck 1 cycle 3 assign busy 0 assign camin 5\h assign pad_qck 0 cycle 30 sim | End of macro file encountered set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector coladdr COLADDR8 COLADDR7 COLADDR6 COLADDR5 COLADDR4 COLADDR3 COLADDR2 COLADDR1 COLADDR0 radix hex coladdr vector camin PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 radix hex camin vector rowaddr ROWADDR8 ROWADDR7 ROWADDR6 ROWADDR5 ROWADDR4 ROWADDR3 ROWADDR2 ROWADDR1 ROWADDR0 radix hex rowaddr vector camout CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 radix hex camout | Watched Signals and Vectors | | Define your signal and vector watch list here watch rowaddr camout coladdr watch camin WRITE CLK BUSY READFIFO EMPTY PAD_FST PAD_QCK WRFIFO assign pad_qck 0 assign pad_fst 0 assign busy 0 assign camin 0\h cycle assign pad_fst 1 cycle 4 assign pad_fst 0 cycle 4 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 3\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 2\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 1\h cycle 1 assign pad_qck 1 |assign busy 1 cycle 1 assign busy 1 cycle 2 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 6\h assign pad_qck 0 cycle 3 assign camin 5\h assign pad_qck 1 cycle 3 assign busy 0 assign camin 5\h assign pad_qck 0 cycle 30 sim | End of macro file encountered set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector coladdr COLADDR8 COLADDR7 COLADDR6 COLADDR5 COLADDR4 COLADDR3 COLADDR2 COLADDR1 COLADDR0 radix hex coladdr vector camin PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 radix hex camin vector rowaddr ROWADDR8 ROWADDR7 ROWADDR6 ROWADDR5 ROWADDR4 ROWADDR3 ROWADDR2 ROWADDR1 ROWADDR0 radix hex rowaddr vector camout CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 radix hex camout | Watched Signals and Vectors | | Define your signal and vector watch list here watch rowaddr camout coladdr watch camin WRITE CLK BUSY READFIFO EMPTY PAD_FST PAD_QCK WRFIFO assign pad_qck 0 assign pad_fst 0 assign busy 0 assign camin 0\h cycle assign pad_fst 1 cycle 4 assign pad_fst 0 cycle 4 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 3\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 2\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 1\h cycle 1 assign pad_qck 1 |assign busy 1 cycle 1 assign busy 1 cycle 2 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 6\h assign pad_qck 0 cycle 3 assign camin 5\h assign pad_qck 1 cycle 3 assign busy 0 assign camin 5\h assign pad_qck 0 cycle 30 sim | End of macro file encountered set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector coladdr COLADDR8 COLADDR7 COLADDR6 COLADDR5 COLADDR4 COLADDR3 COLADDR2 COLADDR1 COLADDR0 radix hex coladdr vector camin PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 radix hex camin vector rowaddr ROWADDR8 ROWADDR7 ROWADDR6 ROWADDR5 ROWADDR4 ROWADDR3 ROWADDR2 ROWADDR1 ROWADDR0 radix hex rowaddr vector camout CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 radix hex camout | Watched Signals and Vectors | | Define your signal and vector watch list here watch rowaddr camout coladdr watch camin WRITE CLK BUSY READFIFO EMPTY PAD_FST PAD_QCK WRFIFO assign pad_qck 0 assign pad_fst 0 assign busy 0 assign camin 0\h cycle assign pad_fst 1 cycle 4 assign pad_fst 0 cycle 4 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 3\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 2\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 1\h cycle 1 assign pad_qck 1 |assign busy 1 cycle 1 assign busy 1 cycle 2 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 6\h assign pad_qck 0 cycle 3 assign camin 5\h assign pad_qck 1 cycle 3 assign busy 0 assign camin 5\h assign pad_qck 0 cycle 30 sim | End of macro file encountered set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector datain datain7 datain6 datain5 datain4 datain3 datain2 datain1 datain0 radix hex datain vector dataout dataout7 dataout 6 dataout5 dataout4 dataout3 dataout2 dataout1 dataout0 | Unknown signal or pin name: dataout - ignored | Unknown signal or pin name: 6 - ignored radix hex dataout | Watched Signals and Vectors | | Define your signal and vector watch list here watch datain dataout clk empty read write |watch datain WRITE CLK BUSY READFIFO EMPTY PAD_FST PAD_QCK WRFIFO assign write 0 assign read 0 assign datain 0\h cycle assign write 1 assign read 0 assign datain 5\h cycle assign write 0 assign read 1 assign datain 0\h cycle assign write 1 assign read 0 assign datain 4\h cycle assign write 1 assign read 1 assign datain 0\h cycle assign write 0 assign read 1 assign datain 0\h cycle sim | End of macro file encountered set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector datain datain7 datain6 datain5 datain4 datain3 datain2 datain1 datain0 radix hex datain vector dataout dataout7 dataout 6 dataout5 dataout4 dataout3 dataout2 dataout1 dataout0 | Unknown signal or pin name: dataout - ignored | Unknown signal or pin name: 6 - ignored radix hex dataout | Watched Signals and Vectors | | Define your signal and vector watch list here watch datain dataout clk empty read write assign write 0 assign read 0 assign datain 0\h cycle assign write 1 assign read 0 assign datain 5\h cycle assign write 0 assign read 1 assign datain 0\h cycle assign write 1 assign read 0 assign datain 4\h cycle assign write 1 assign read 1 assign datain 0\h cycle assign write 0 assign read 1 assign datain 0\h cycle sim | End of macro file encountered | The file has been automatically generated by | the Script Editor File Wizard version 2.0.1.89 | | Copyright | Initial settings delete_signals clpr log | Removing existing log file log log | Macro log file Z:\AMMERMAN\CSE567\WORKING\VGACAM\log.log is already opened set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector datain datain7 datain6 datain5 datain4 datain3 datain2 datain1 datain0 radix hex datain vector dataout dataout7 dataout6 dataout5 dataout4 dataout3 dataout2 dataout1 dataout0 radix hex dataout vector wr_addr wr_addr7 wr_addr6 wr_addr5 wr_addr4 wr_addr3 wr_addr2 wr_addr1 wr_addr0 | Unknown signal or pin name: wr_addr7 - ignored | Unknown signal or pin name: wr_addr6 - ignored | Unknown signal or pin name: wr_addr5 - ignored | Unknown signal or pin name: wr_addr4 - ignored | Unknown signal or pin name: wr_addr3 - ignored | Unknown signal or pin name: wr_addr2 - ignored | Unknown signal or pin name: wr_addr1 - ignored | Unknown signal or pin name: wr_addr0 - ignored radix hex wr_addr | Incorrect signal or pin name: wr_addr vector re_addr re_addr7 re_addr6 re_addr5 re_addr4 re_addr3 re_addr2 re_addr1 re_addr0 | Unknown signal or pin name: re_addr7 - ignored | Unknown signal or pin name: re_addr6 - ignored | Unknown signal or pin name: re_addr5 - ignored | Unknown signal or pin name: re_addr4 - ignored | Unknown signal or pin name: re_addr3 - ignored | Unknown signal or pin name: re_addr2 - ignored | Unknown signal or pin name: re_addr1 - ignored | Unknown signal or pin name: re_addr0 - ignored radix hex re_addr | Incorrect signal or pin name: re_addr | Watched Signals and Vectors | | Define your signal and vector watch list here watch datain dataout clk empty read write re_addr wr_addr | Incorrect signal or pin name: re_addr | Incorrect signal or pin name: wr_addr assign write 0 assign read 0 assign datain 0\h cycle assign write 1 assign read 0 assign datain 5\h cycle assign write 0 assign read 1 assign datain 0\h cycle assign write 1 assign read 0 assign datain 4\h cycle assign write 1 assign read 1 assign datain 0\h cycle assign write 0 assign read 1 assign datain 0\h cycle sim | End of macro file encountered | The file has been automatically generated by | the Script Editor File Wizard version 2.0.1.89 | | Copyright | Initial settings delete_signals clpr log | Removing existing log file log log | Macro log file Z:\AMMERMAN\CSE567\WORKING\VGACAM\log.log is already opened set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector datain datain7 datain6 datain5 datain4 datain3 datain2 datain1 datain0 radix hex datain vector dataout dataout7 dataout6 dataout5 dataout4 dataout3 dataout2 dataout1 dataout0 radix hex dataout vector wr_cnt wr_cnt7 wr_cnt6 wr_cnt5 wr_cnt4 wr_cnt3 wr_cnt2 wr_cnt1 wr_cnt0 radix hex wr_cnt vector re_cnt re_cnt7 re_cnt6 re_cnt5 re_cnt4 re_cnt3 re_cnt2 re_cnt1 re_cnt0 radix hex re_cnt | Watched Signals and Vectors | | Define your signal and vector watch list here watch datain dataout clk empty read write re_cnt wr_cnt assign write 0 assign read 0 assign datain 0\h cycle assign write 1 assign read 0 assign datain 5\h cycle assign write 0 assign read 1 assign datain 0\h cycle assign write 1 assign read 0 assign datain 4\h cycle assign write 1 assign read 1 assign datain 0\h cycle assign write 0 assign read 1 assign datain 0\h cycle sim | End of macro file encountered | The file has been automatically generated by | the Script Editor File Wizard version 2.0.1.89 | | Copyright | Initial settings delete_signals clpr log | Removing existing log file log log | Macro log file Z:\AMMERMAN\CSE567\WORKING\VGACAM\log.log is already opened set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector datain datain7 datain6 datain5 datain4 datain3 datain2 datain1 datain0 radix hex datain vector dataout dataout7 dataout6 dataout5 dataout4 dataout3 dataout2 dataout1 dataout0 radix hex dataout vector wr_cnt wr_cnt7 wr_cnt6 wr_cnt5 wr_cnt4 wr_cnt3 wr_cnt2 wr_cnt1 wr_cnt0 radix hex wr_cnt vector re_cnt re_cnt7 re_cnt6 re_cnt5 re_cnt4 re_cnt3 re_cnt2 re_cnt1 re_cnt0 radix hex re_cnt | Watched Signals and Vectors | | Define your signal and vector watch list here watch datain dataout clk empty read write re_cnt wr_cnt reset assign reset 0 assign write 0 assign read 0 assign datain 0\h cycle assign write 1 assign read 0 assign datain 5\h cycle assign write 0 assign read 1 assign datain 0\h cycle assign write 1 assign read 0 assign datain 4\h cycle assign write 1 assign read 1 assign datain 0\h cycle assign write 0 assign read 1 assign datain 0\h cycle sim | End of macro file encountered | The file has been automatically generated by | the Script Editor File Wizard version 2.0.1.89 | | Copyright | Initial settings delete_signals clpr log | Removing existing log file log log | Macro log file Z:\AMMERMAN\CSE567\WORKING\VGACAM\log.log is already opened set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector datain datain7 datain6 datain5 datain4 datain3 datain2 datain1 datain0 radix hex datain vector dataout dataout7 dataout6 dataout5 dataout4 dataout3 dataout2 dataout1 dataout0 radix hex dataout vector wr_cnt wr_cnt7 wr_cnt6 wr_cnt5 wr_cnt4 wr_cnt3 wr_cnt2 wr_cnt1 wr_cnt0 radix hex wr_cnt vector re_cnt re_cnt7 re_cnt6 re_cnt5 re_cnt4 re_cnt3 re_cnt2 re_cnt1 re_cnt0 radix hex re_cnt | Watched Signals and Vectors | | Define your signal and vector watch list here watch datain dataout clk empty read write re_cnt wr_cnt reset assign reset 0 assign write 0 assign read 0 assign datain 1\h cycle assign write 1 assign read 0 assign datain 2\h cycle assign write 0 assign read 1 assign datain 3\h cycle assign write 1 assign read 0 assign datain 4\h cycle assign write 1 assign read 1 assign datain 5\h cycle assign write 0 assign read 1 assign datain 6\h cycle sim | End of macro file encountered set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector datain datain7 datain6 datain5 datain4 datain3 datain2 datain1 datain0 radix hex datain vector dataout dataout7 dataout6 dataout5 dataout4 dataout3 dataout2 dataout1 dataout0 radix hex dataout vector wr_cnt wr_cnt7 wr_cnt6 wr_cnt5 wr_cnt4 wr_cnt3 wr_cnt2 wr_cnt1 wr_cnt0 radix hex wr_cnt vector re_cnt re_cnt7 re_cnt6 re_cnt5 re_cnt4 re_cnt3 re_cnt2 re_cnt1 re_cnt0 radix hex re_cnt | Watched Signals and Vectors | | Define your signal and vector watch list here watch datain dataout clk empty read write reset assign reset 0 assign write 0 assign read 0 assign datain 1\h cycle assign write 1 assign read 0 assign datain 2\h cycle assign write 0 assign read 1 assign datain 3\h cycle assign write 1 assign read 0 assign datain 4\h cycle assign write 1 assign read 1 assign datain 5\h cycle assign write 0 assign read 1 assign datain 6\h cycle sim | End of macro file encountered | The file has been automatically generated by | the Script Editor File Wizard version 2.0.1.89 | | Copyright | Initial settings delete_signals clpr log | Removing existing log file log log | Macro log file Z:\AMMERMAN\CSE567\WORKING\VGACAM\log.log is already opened set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector datain datain7 datain6 datain5 datain4 datain3 datain2 datain1 datain0 radix hex datain vector dataout dataout7 dataout6 dataout5 dataout4 dataout3 dataout2 dataout1 dataout0 radix hex dataout vector wr_cnt wr_cnt7 wr_cnt6 wr_cnt5 wr_cnt4 wr_cnt3 wr_cnt2 wr_cnt1 wr_cnt0 radix hex wr_cnt vector re_cnt re_cnt7 re_cnt6 re_cnt5 re_cnt4 re_cnt3 re_cnt2 re_cnt1 re_cnt0 radix hex re_cnt | Watched Signals and Vectors | | Define your signal and vector watch list here watch datain dataout clk empty read write reset assign reset 1 assign write 0 assign read 0 assign datain 1\h cycle assign reset 0 assign write 0 assign read 0 assign datain 1\h cycle assign write 1 assign read 0 assign datain 2\h cycle assign write 0 assign read 1 assign datain 3\h cycle assign write 1 assign read 0 assign datain 4\h cycle assign write 1 assign read 1 assign datain 5\h cycle assign write 0 assign read 1 assign datain 6\h cycle sim | End of macro file encountered set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector datain datain7 datain6 datain5 datain4 datain3 datain2 datain1 datain0 radix hex datain vector dataout dataout7 dataout6 dataout5 dataout4 dataout3 dataout2 dataout1 dataout0 radix hex dataout vector wr_cnt wr_cnt7 wr_cnt6 wr_cnt5 wr_cnt4 wr_cnt3 wr_cnt2 wr_cnt1 wr_cnt0 radix hex wr_cnt vector re_cnt re_cnt7 re_cnt6 re_cnt5 re_cnt4 re_cnt3 re_cnt2 re_cnt1 re_cnt0 radix hex re_cnt | Watched Signals and Vectors | | Define your signal and vector watch list here watch datain dataout clk empty read write reset assign reset 1 assign write 0 assign read 0 assign datain 1\h cycle assign reset 0 assign write 0 assign read 0 assign datain 1\h cycle assign write 1 assign read 0 assign datain 2\h cycle assign write 0 assign read 1 assign datain 3\h cycle assign write 1 assign read 0 assign datain 4\h cycle assign write 1 assign read 1 assign datain 5\h cycle assign write 0 assign read 1 assign datain 6\h cycle sim | End of macro file encountered | The file has been automatically generated by | the Script Editor File Wizard version 2.0.1.89 | | Copyright | Initial settings delete_signals clpr log | Removing existing log file log log | Macro log file Z:\AMMERMAN\CSE567\WORKING\VGACAM\log.log is already opened set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector datain datain7 datain6 datain5 datain4 datain3 datain2 datain1 datain0 radix hex datain vector dataout dataout7 dataout6 dataout5 dataout4 dataout3 dataout2 dataout1 dataout0 radix hex dataout vector wr_cnt wr_cnt7 wr_cnt6 wr_cnt5 wr_cnt4 wr_cnt3 wr_cnt2 wr_cnt1 wr_cnt0 radix hex wr_cnt vector re_cnt re_cnt7 re_cnt6 re_cnt5 re_cnt4 re_cnt3 re_cnt2 re_cnt1 re_cnt0 radix hex re_cnt | Watched Signals and Vectors | | Define your signal and vector watch list here watch datain dataout clk empty read write reset wr_cnt re_cnt assign reset 1 assign write 0 assign read 0 assign datain 1\h cycle assign reset 1 assign write 0 assign read 0 assign datain 1\h cycle assign reset 0 assign write 0 assign read 0 assign datain 1\h cycle assign write 1 assign read 0 assign datain 2\h cycle assign write 0 assign read 1 assign datain 3\h cycle assign write 1 assign read 0 assign datain 4\h cycle assign write 1 assign read 1 assign datain 5\h cycle assign write 0 assign read 1 assign datain 6\h cycle sim | End of macro file encountered | The file has been automatically generated by | the Script Editor File Wizard version 2.0.1.89 | | Copyright | Initial settings delete_signals clpr log | Removing existing log file log log | Macro log file Z:\AMMERMAN\CSE567\WORKING\VGACAM\log.log is already opened set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector datain datain7 datain6 datain5 datain4 datain3 datain2 datain1 datain0 radix hex datain vector dataout dataout7 dataout6 dataout5 dataout4 dataout3 dataout2 dataout1 dataout0 radix hex dataout vector wr_cnt wr_cnt7 wr_cnt6 wr_cnt5 wr_cnt4 wr_cnt3 wr_cnt2 wr_cnt1 wr_cnt0 radix hex wr_cnt vector re_cnt re_cnt7 re_cnt6 re_cnt5 re_cnt4 re_cnt3 re_cnt2 re_cnt1 re_cnt0 radix hex re_cnt | Watched Signals and Vectors | | Define your signal and vector watch list here watch datain dataout clk empty read write reset wr_cnt re_cnt assign reset 0 assign write 0 assign read 0 assign datain 1\h cycle assign reset 1 assign write 0 assign read 0 assign datain 1\h cycle assign reset 0 assign write 0 assign read 0 assign datain 1\h cycle assign write 1 assign read 0 assign datain 2\h cycle assign write 0 assign read 1 assign datain 3\h cycle assign write 1 assign read 0 assign datain 4\h cycle assign write 1 assign read 1 assign datain 5\h cycle assign write 0 assign read 1 assign datain 6\h cycle sim | End of macro file encountered set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector datain datain7 datain6 datain5 datain4 datain3 datain2 datain1 datain0 radix hex datain vector dataout dataout7 dataout6 dataout5 dataout4 dataout3 dataout2 dataout1 dataout0 radix hex dataout vector wr_cnt wr_cnt7 wr_cnt6 wr_cnt5 wr_cnt4 wr_cnt3 wr_cnt2 wr_cnt1 wr_cnt0 radix hex wr_cnt vector re_cnt re_cnt7 re_cnt6 re_cnt5 re_cnt4 re_cnt3 re_cnt2 re_cnt1 re_cnt0 radix hex re_cnt | Watched Signals and Vectors | | Define your signal and vector watch list here watch datain dataout clk empty read write reset wr_cnt re_cnt assign reset 0 assign write 0 assign read 0 assign datain 1\h cycle assign reset 1 assign write 0 assign read 0 assign datain 1\h cycle assign reset 0 assign write 0 assign read 0 assign datain 1\h cycle assign write 1 assign read 0 assign datain 2\h cycle assign write 0 assign read 1 assign datain 3\h cycle assign write 1 assign read 0 assign datain 4\h cycle assign write 1 assign read 1 assign datain 5\h cycle assign write 0 assign read 1 assign datain 6\h cycle sim | End of macro file encountered set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector datain datain7 datain6 datain5 datain4 datain3 datain2 datain1 datain0 radix hex datain vector dataout dataout7 dataout6 dataout5 dataout4 dataout3 dataout2 dataout1 dataout0 radix hex dataout vector wr_cnt wr_cnt7 wr_cnt6 wr_cnt5 wr_cnt4 wr_cnt3 wr_cnt2 wr_cnt1 wr_cnt0 radix hex wr_cnt vector re_cnt re_cnt7 re_cnt6 re_cnt5 re_cnt4 re_cnt3 re_cnt2 re_cnt1 re_cnt0 radix hex re_cnt | Watched Signals and Vectors | | Define your signal and vector watch list here watch datain dataout clk empty read write reset wr_cnt re_cnt assign reset 0 assign write 0 assign read 0 assign datain 1\h cycle assign reset 1 assign write 0 assign read 0 assign datain 1\h cycle assign reset 0 assign write 0 assign read 0 assign datain 1\h cycle assign write 1 assign read 0 assign datain 2\h cycle assign write 0 assign read 1 assign datain 3\h cycle assign write 1 assign read 0 assign datain 4\h cycle assign write 1 assign read 1 assign datain 5\h cycle assign write 0 assign read 1 assign datain 6\h cycle sim | End of macro file encountered | The file has been automatically generated by | the Script Editor File Wizard version 2.0.1.89 | | Copyright | Initial settings delete_signals clpr log | Removing existing log file log log | Macro log file Z:\AMMERMAN\CSE567\WORKING\VGACAM\log.log is already opened set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector datain datain7 datain6 datain5 datain4 datain3 datain2 datain1 datain0 radix hex datain vector dataout dataout7 dataout6 dataout5 dataout4 dataout3 dataout2 dataout1 dataout0 radix hex dataout vector wr_cnt wr_cnt7 wr_cnt6 wr_cnt5 wr_cnt4 wr_cnt3 wr_cnt2 wr_cnt1 wr_cnt0 radix hex wr_cnt vector re_cnt re_cnt7 re_cnt6 re_cnt5 re_cnt4 re_cnt3 re_cnt2 re_cnt1 re_cnt0 radix hex re_cnt | Watched Signals and Vectors | | Define your signal and vector watch list here watch datain dataout clk empty read write reset wr_cnt re_cnt assign reset 1 assign write 0 assign read 0 assign datain 1\h cycle assign reset 0 assign write 0 assign read 0 assign datain 1\h cycle assign write 1 assign read 0 assign datain 2\h cycle assign write 0 assign read 1 assign datain 3\h cycle assign write 1 assign read 0 assign datain 4\h cycle assign write 1 assign read 1 assign datain 5\h cycle assign write 0 assign read 1 assign datain 6\h cycle sim | End of macro file encountered | The file has been automatically generated by | the Script Editor File Wizard version 2.0.1.89 | | Copyright | Initial settings delete_signals clpr log | Removing existing log file log log | Macro log file Z:\AMMERMAN\CSE567\WORKING\VGACAM\log.log is already opened set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector datain datain7 datain6 datain5 datain4 datain3 datain2 datain1 datain0 radix hex datain vector dataout dataout7 dataout6 dataout5 dataout4 dataout3 dataout2 dataout1 dataout0 radix hex dataout vector wr_cnt wr_cnt7 wr_cnt6 wr_cnt5 wr_cnt4 wr_cnt3 wr_cnt2 wr_cnt1 wr_cnt0 radix hex wr_cnt vector re_cnt re_cnt7 re_cnt6 re_cnt5 re_cnt4 re_cnt3 re_cnt2 re_cnt1 re_cnt0 radix hex re_cnt | Watched Signals and Vectors | | Define your signal and vector watch list here watch datain dataout clk empty read write reset wr_cnt re_cnt assign reset 0 assign write 0 assign read 0 assign datain 1\h cycle assign reset 1 assign write 0 assign read 0 assign datain 1\h cycle assign reset 0 assign write 0 assign read 0 assign datain 1\h cycle assign write 1 assign read 0 assign datain 2\h cycle assign write 0 assign read 1 assign datain 3\h cycle assign write 1 assign read 0 assign datain 4\h cycle assign write 1 assign read 1 assign datain 5\h cycle assign write 0 assign read 1 assign datain 6\h cycle sim | End of macro file encountered set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector datain datain7 datain6 datain5 datain4 datain3 datain2 datain1 datain0 radix hex datain vector dataout dataout7 dataout6 dataout5 dataout4 dataout3 dataout2 dataout1 dataout0 radix hex dataout vector wr_cnt wr_cnt7 wr_cnt6 wr_cnt5 wr_cnt4 wr_cnt3 wr_cnt2 wr_cnt1 wr_cnt0 | Unknown signal or pin name: wr_cnt7 - ignored | Unknown signal or pin name: wr_cnt6 - ignored | Unknown signal or pin name: wr_cnt5 - ignored | Unknown signal or pin name: wr_cnt4 - ignored | Unknown signal or pin name: wr_cnt3 - ignored | Unknown signal or pin name: wr_cnt2 - ignored | Unknown signal or pin name: wr_cnt1 - ignored | Unknown signal or pin name: wr_cnt0 - ignored radix hex wr_cnt | Incorrect signal or pin name: wr_cnt vector re_cnt re_cnt7 re_cnt6 re_cnt5 re_cnt4 re_cnt3 re_cnt2 re_cnt1 re_cnt0 radix hex re_cnt | Watched Signals and Vectors | | Define your signal and vector watch list here watch datain dataout clk empty read write reset wr_cnt re_cnt | Incorrect signal or pin name: wr_cnt assign reset 0 assign write 0 assign read 0 assign datain 1\h cycle assign reset 1 assign write 0 assign read 0 assign datain 1\h cycle assign reset 0 assign write 0 assign read 0 assign datain 1\h cycle assign write 1 assign read 0 assign datain 2\h cycle assign write 0 assign read 1 assign datain 3\h cycle assign write 1 assign read 0 assign datain 4\h cycle assign write 1 assign read 1 assign datain 5\h cycle assign write 0 assign read 1 assign datain 6\h cycle sim | End of macro file encountered set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector coladdr COLADDR8 COLADDR7 COLADDR6 COLADDR5 COLADDR4 COLADDR3 COLADDR2 COLADDR1 COLADDR0 radix hex coladdr vector camin PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 radix hex camin vector rowaddr ROWADDR8 ROWADDR7 ROWADDR6 ROWADDR5 ROWADDR4 ROWADDR3 ROWADDR2 ROWADDR1 ROWADDR0 radix hex rowaddr vector camout CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 radix hex camout | Watched Signals and Vectors | | Define your signal and vector watch list here watch rowaddr coladdr camin camout watch write clk busy readfifo empty pad_fst pad_qck wrfifo assign pad_qck 0 assign pad_fst 0 assign busy 0 assign camin 0\h cycle assign pad_fst 1 cycle 4 assign pad_fst 0 cycle 4 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 3\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 2\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 1\h cycle 1 assign pad_qck 1 cycle 1 assign busy 1 cycle 2 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 6\h assign pad_qck 0 cycle 3 assign camin 5\h assign pad_qck 1 cycle 3 assign busy 0 assign camin 5\h assign pad_qck 0 cycle 30 sim | End of macro file encountered set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector coladdr COLADDR8 COLADDR7 COLADDR6 COLADDR5 COLADDR4 COLADDR3 COLADDR2 COLADDR1 COLADDR0 radix hex coladdr vector camin PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 | Unknown signal or pin name: PAD_CAM3 - ignored | Unknown signal or pin name: PAD_CAM2 - ignored | Unknown signal or pin name: PAD_CAM1 - ignored | Unknown signal or pin name: PAD_CAM0 - ignored radix hex camin | Incorrect signal or pin name: camin vector rowaddr ROWADDR8 ROWADDR7 ROWADDR6 ROWADDR5 ROWADDR4 ROWADDR3 ROWADDR2 ROWADDR1 ROWADDR0 radix hex rowaddr vector camout CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 | Unknown signal or pin name: CAMDATAOUT7 - ignored | Unknown signal or pin name: CAMDATAOUT6 - ignored | Unknown signal or pin name: CAMDATAOUT5 - ignored | Unknown signal or pin name: CAMDATAOUT4 - ignored | Unknown signal or pin name: CAMDATAOUT3 - ignored | Unknown signal or pin name: CAMDATAOUT2 - ignored | Unknown signal or pin name: CAMDATAOUT1 - ignored | Unknown signal or pin name: CAMDATAOUT0 - ignored radix hex camout | Incorrect signal or pin name: camout | Watched Signals and Vectors | | Define your signal and vector watch list here watch rowaddr coladdr camin camout | Incorrect signal or pin name: camin | Incorrect signal or pin name: camout watch write clk busy readfifo empty pad_fst pad_qck wrfifo | Incorrect signal or pin name: write | Incorrect signal or pin name: busy | Incorrect signal or pin name: readfifo | Incorrect signal or pin name: empty | Incorrect signal or pin name: pad_fst | Incorrect signal or pin name: pad_qck | Incorrect signal or pin name: wrfifo assign pad_qck 0 | Incorrect signal or pin name: pad_qck assign pad_fst 0 | Incorrect signal or pin name: pad_fst assign busy 0 | Incorrect signal or pin name: busy assign camin 0\h | Incorrect signal or pin name: camin cycle assign pad_fst 1 | Incorrect signal or pin name: pad_fst cycle 4 assign pad_fst 0 | Incorrect signal or pin name: pad_fst cycle 4 assign camin 5\h | Incorrect signal or pin name: camin cycle 1 assign pad_qck 1 | Incorrect signal or pin name: pad_qck cycle 3 assign camin 2\h | Incorrect signal or pin name: camin cycle 1 assign pad_qck 0 | Incorrect signal or pin name: pad_qck cycle 3 assign camin 3\h | Incorrect signal or pin name: camin cycle 1 assign pad_qck 1 | Incorrect signal or pin name: pad_qck cycle 3 assign camin 1\h | Incorrect signal or pin name: camin cycle 1 assign pad_qck 0 | Incorrect signal or pin name: pad_qck cycle 3 assign camin 2\h | Incorrect signal or pin name: camin cycle 1 assign pad_qck 1 | Incorrect signal or pin name: pad_qck cycle 3 assign camin 1\h | Incorrect signal or pin name: camin cycle 1 assign pad_qck 0 | Incorrect signal or pin name: pad_qck cycle 3 assign camin 1\h | Incorrect signal or pin name: camin cycle 1 assign pad_qck 1 | Incorrect signal or pin name: pad_qck cycle 1 assign busy 1 | Incorrect signal or pin name: busy cycle 2 assign camin 2\h | Incorrect signal or pin name: camin cycle 1 assign pad_qck 0 | Incorrect signal or pin name: pad_qck cycle 3 assign camin 5\h | Incorrect signal or pin name: camin cycle 1 assign pad_qck 1 | Incorrect signal or pin name: pad_qck cycle 3 assign camin 6\h | Incorrect signal or pin name: camin assign pad_qck 0 | Incorrect signal or pin name: pad_qck cycle 3 assign camin 5\h | Incorrect signal or pin name: camin assign pad_qck 1 | Incorrect signal or pin name: pad_qck cycle 3 assign busy 0 | Incorrect signal or pin name: busy assign camin 5\h | Incorrect signal or pin name: camin assign pad_qck 0 | Incorrect signal or pin name: pad_qck cycle 30 sim | End of macro file encountered | The file has been automatically generated by | the Script Editor File Wizard version 2.0.1.89 | | Copyright | Initial settings delete_signals clpr log | Removing existing log file log log | Macro log file Z:\AMMERMAN\CSE567\WORKING\VGACAM\log.log is already opened set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector coladdr COLADDR8 COLADDR7 COLADDR6 COLADDR5 COLADDR4 COLADDR3 COLADDR2 COLADDR1 COLADDR0 radix hex coladdr vector camin PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 radix hex camin vector rowaddr ROWADDR8 ROWADDR7 ROWADDR6 ROWADDR5 ROWADDR4 ROWADDR3 ROWADDR2 ROWADDR1 ROWADDR0 radix hex rowaddr vector camout CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 radix hex camout | Watched Signals and Vectors | | Define your signal and vector watch list here watch rowaddr coladdr camin camout watch write clk busy readfifo empty pad_fst pad_qck wrfifo assign pad_qck 0 assign pad_fst 0 assign busy 0 assign camin 0\h cycle assign pad_fst 1 cycle 4 assign pad_fst 0 cycle 4 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 3\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 2\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 1\h cycle 1 assign pad_qck 1 cycle 1 assign busy 1 cycle 2 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 6\h assign pad_qck 0 cycle 3 assign camin 5\h assign pad_qck 1 cycle 3 assign busy 0 assign camin 5\h assign pad_qck 0 cycle 30 sim | End of macro file encountered set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector datain datain7 datain6 datain5 datain4 datain3 datain2 datain1 datain0 radix hex datain vector dataout dataout7 dataout6 dataout5 dataout4 dataout3 dataout2 dataout1 dataout0 radix hex dataout vector wr_cnt wr_cnt7 wr_cnt6 wr_cnt5 wr_cnt4 wr_cnt3 wr_cnt2 wr_cnt1 wr_cnt0 radix hex wr_cnt vector re_cnt re_cnt7 re_cnt6 re_cnt5 re_cnt4 re_cnt3 re_cnt2 re_cnt1 re_cnt0 radix hex re_cnt | Watched Signals and Vectors | | Define your signal and vector watch list here watch datain dataout clk empty read write reset wr_cnt re_cnt assign reset 0 assign write 0 assign read 0 assign datain 1\h cycle assign reset 1 assign write 0 assign read 0 assign datain 1\h cycle assign reset 0 assign write 0 assign read 0 assign datain 1\h cycle assign write 1 assign read 0 assign datain 2\h cycle assign write 0 assign read 1 assign datain 3\h cycle assign write 1 assign read 0 assign datain 4\h cycle assign write 1 assign read 1 assign datain 5\h cycle assign write 0 assign read 1 assign datain 6\h cycle sim | End of macro file encountered | The file has been automatically generated by | the Script Editor File Wizard version 2.0.1.89 | | Copyright | Initial settings delete_signals clpr log | Removing existing log file log log | Macro log file Z:\AMMERMAN\CSE567\WORKING\VGACAM\log.log is already opened set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector coladdr COLADDR8 COLADDR7 COLADDR6 COLADDR5 COLADDR4 COLADDR3 COLADDR2 COLADDR1 COLADDR0 radix hex coladdr vector camin PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 radix hex camin vector rowaddr ROWADDR8 ROWADDR7 ROWADDR6 ROWADDR5 ROWADDR4 ROWADDR3 ROWADDR2 ROWADDR1 ROWADDR0 radix hex rowaddr vector camout CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 radix hex camout | Watched Signals and Vectors | | Define your signal and vector watch list here watch rowaddr coladdr camin camout watch write busy pad_fst pad_qck watch wrfifo readfifo empty clk assign pad_qck 0 assign pad_fst 0 assign busy 0 assign camin 0\h cycle assign pad_fst 1 cycle 4 assign pad_fst 0 cycle 4 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 3\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 2\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 1\h cycle 1 assign pad_qck 1 cycle 1 assign busy 1 cycle 2 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 6\h assign pad_qck 0 cycle 3 assign camin 5\h assign pad_qck 1 cycle 3 assign busy 0 assign camin 5\h assign pad_qck 0 cycle 30 sim | End of macro file encountered | The file has been automatically generated by | the Script Editor File Wizard version 2.0.1.89 | | Copyright | Initial settings delete_signals clpr log | Removing existing log file log log | Macro log file Z:\AMMERMAN\CSE567\WORKING\VGACAM\log.log is already opened set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector coladdr COLADDR8 COLADDR7 COLADDR6 COLADDR5 COLADDR4 COLADDR3 COLADDR2 COLADDR1 COLADDR0 radix hex coladdr vector camin PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 radix hex camin vector rowaddr ROWADDR8 ROWADDR7 ROWADDR6 ROWADDR5 ROWADDR4 ROWADDR3 ROWADDR2 ROWADDR1 ROWADDR0 radix hex rowaddr vector camout CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 radix hex camout | Watched Signals and Vectors | | Define your signal and vector watch list here watch camin pad_fst pad_qck busy write watch camout rowaddr coladdr watch wrfifo readfifo empty clk assign pad_qck 0 assign pad_fst 0 assign busy 0 assign camin 0\h cycle assign pad_fst 1 cycle 4 assign pad_fst 0 cycle 4 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 3\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 2\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 1\h cycle 1 assign pad_qck 1 cycle 1 assign busy 1 cycle 2 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 6\h assign pad_qck 0 cycle 3 assign camin 5\h assign pad_qck 1 cycle 3 assign busy 0 assign camin 5\h assign pad_qck 0 cycle 30 sim | End of macro file encountered set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector coladdr COLADDR8 COLADDR7 COLADDR6 COLADDR5 COLADDR4 COLADDR3 COLADDR2 COLADDR1 COLADDR0 radix hex coladdr vector camin PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 radix hex camin vector rowaddr ROWADDR8 ROWADDR7 ROWADDR6 ROWADDR5 ROWADDR4 ROWADDR3 ROWADDR2 ROWADDR1 ROWADDR0 radix hex rowaddr vector camout CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 radix hex camout | Watched Signals and Vectors | | Define your signal and vector watch list here watch camin pad_fst pad_qck busy write watch camout rowaddr coladdr watch wrfifo readfifo empty clk assign pad_qck 0 assign pad_fst 0 assign busy 0 assign camin 0\h cycle assign pad_fst 1 cycle 4 assign pad_fst 0 cycle 4 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 3\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 2\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 1\h cycle 1 assign pad_qck 1 cycle 1 assign busy 1 cycle 2 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 6\h assign pad_qck 0 cycle 3 assign camin 5\h assign pad_qck 1 cycle 3 assign busy 0 assign camin 5\h assign pad_qck 0 cycle 30 sim | End of macro file encountered | The file has been automatically generated by | the Script Editor File Wizard version 2.0.1.89 | | Copyright | Initial settings delete_signals clpr log | Removing existing log file log log | Macro log file Z:\AMMERMAN\CSE567\WORKING\VGACAM\log.log is already opened set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector datain datain7 datain6 datain5 datain4 datain3 datain2 datain1 datain0 radix hex datain vector dataout dataout7 dataout6 dataout5 dataout4 dataout3 dataout2 dataout1 dataout0 radix hex dataout vector wr_cnt wr_cnt7 wr_cnt6 wr_cnt5 wr_cnt4 wr_cnt3 wr_cnt2 wr_cnt1 wr_cnt0 radix hex wr_cnt vector re_cnt re_cnt7 re_cnt6 re_cnt5 re_cnt4 re_cnt3 re_cnt2 re_cnt1 re_cnt0 radix hex re_cnt | Watched Signals and Vectors | | Define your signal and vector watch list here watch datain dataout clk empty read write reset wr_cnt re_cnt assign reset 0 assign write 0 assign read 0 assign datain 1\h cycle assign reset 1 assign write 0 assign read 0 assign datain 1\h cycle assign reset 0 assign write 0 assign read 0 assign datain 1\h cycle assign write 1 assign read 0 assign datain 2\h cycle assign write 0 assign read 1 assign datain 3\h cycle assign write 1 assign read 0 assign datain 4\h cycle assign write 1 assign read 1 assign datain 5\h cycle assign write 0 assign read 1 assign datain 6\h cycle sim | End of macro file encountered | The file has been automatically generated by | the Script Editor File Wizard version 2.0.1.89 | | Copyright | Initial settings delete_signals clpr log | Removing existing log file log log | Macro log file Z:\AMMERMAN\CSE567\WORKING\VGACAM\log.log is already opened set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector coladdr COLADDR8 COLADDR7 COLADDR6 COLADDR5 COLADDR4 COLADDR3 COLADDR2 COLADDR1 COLADDR0 radix hex coladdr vector camin PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 radix hex camin vector rowaddr ROWADDR8 ROWADDR7 ROWADDR6 ROWADDR5 ROWADDR4 ROWADDR3 ROWADDR2 ROWADDR1 ROWADDR0 radix hex rowaddr vector camout CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 radix hex camout | Watched Signals and Vectors | | Define your signal and vector watch list here watch camin pad_fst pad_qck busy write watch camout rowaddr coladdr watch wrfifo readfifo empty clk assign pad_qck 0 assign pad_fst 0 assign busy 0 assign camin 0\h cycle assign pad_fst 1 cycle 4 assign pad_fst 0 cycle 4 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 3\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 2\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 1\h cycle 1 assign pad_qck 1 cycle 1 assign busy 1 cycle 2 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 6\h assign pad_qck 0 cycle 3 assign camin 5\h assign pad_qck 1 cycle 3 assign busy 0 assign camin 5\h assign pad_qck 0 cycle 30 sim | End of macro file encountered set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector coladdr COLADDR8 COLADDR7 COLADDR6 COLADDR5 COLADDR4 COLADDR3 COLADDR2 COLADDR1 COLADDR0 radix hex coladdr vector camin PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 radix hex camin vector rowaddr ROWADDR8 ROWADDR7 ROWADDR6 ROWADDR5 ROWADDR4 ROWADDR3 ROWADDR2 ROWADDR1 ROWADDR0 radix hex rowaddr vector camout CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 radix hex camout | Watched Signals and Vectors | | Define your signal and vector watch list here watch camin pad_fst pad_qck busy write watch camout rowaddr coladdr watch wrfifo readfifo empty clk assign pad_qck 0 assign pad_fst 0 assign busy 0 assign camin 0\h cycle assign pad_fst 1 cycle 4 assign pad_fst 0 cycle 4 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 3\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 2\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 1\h cycle 1 assign pad_qck 1 cycle 1 assign busy 1 cycle 2 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 6\h assign pad_qck 0 cycle 3 assign camin 5\h assign pad_qck 1 cycle 3 assign busy 0 assign camin 5\h assign pad_qck 0 cycle 30 sim | End of macro file encountered set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector coladdr COLADDR8 COLADDR7 COLADDR6 COLADDR5 COLADDR4 COLADDR3 COLADDR2 COLADDR1 COLADDR0 radix hex coladdr vector camin PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 radix hex camin vector rowaddr ROWADDR8 ROWADDR7 ROWADDR6 ROWADDR5 ROWADDR4 ROWADDR3 ROWADDR2 ROWADDR1 ROWADDR0 radix hex rowaddr vector camout CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 radix hex camout | Watched Signals and Vectors | | Define your signal and vector watch list here watch camin pad_fst pad_qck busy write watch camout rowaddr coladdr watch wrfifo readfifo empty clk assign pad_qck 0 assign pad_fst 0 assign busy 0 assign camin 0\h cycle assign pad_fst 1 cycle 4 assign pad_fst 0 cycle 4 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 3\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 2\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 1\h cycle 1 assign pad_qck 1 cycle 1 assign busy 1 cycle 2 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 6\h assign pad_qck 0 cycle 3 assign camin 5\h assign pad_qck 1 cycle 3 assign busy 0 assign camin 5\h assign pad_qck 0 cycle 30 sim | End of macro file encountered | The file has been automatically generated by | the Script Editor File Wizard version 2.0.1.89 | | Copyright | Initial settings delete_signals clpr log | Removing existing log file log log | Macro log file Z:\AMMERMAN\CSE567\WORKING\VGACAM\log.log is already opened set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector datain datain7 datain6 datain5 datain4 datain3 datain2 datain1 datain0 radix hex datain vector dataout dataout7 dataout6 dataout5 dataout4 dataout3 dataout2 dataout1 dataout0 radix hex dataout vector wr_cnt wr_cnt7 wr_cnt6 wr_cnt5 wr_cnt4 wr_cnt3 wr_cnt2 wr_cnt1 wr_cnt0 radix hex wr_cnt vector re_cnt re_cnt7 re_cnt6 re_cnt5 re_cnt4 re_cnt3 re_cnt2 re_cnt1 re_cnt0 radix hex re_cnt | Watched Signals and Vectors | | Define your signal and vector watch list here watch datain dataout clk empty read write reset wr_cnt re_cnt assign reset 0 assign write 0 assign read 0 assign datain 1\h cycle assign reset 1 assign write 0 assign read 0 assign datain 1\h cycle assign reset 0 assign write 0 assign read 0 assign datain 1\h cycle assign write 1 assign read 0 assign datain 2\h cycle assign write 0 assign read 1 assign datain 3\h cycle assign write 1 assign read 0 assign datain 4\h cycle assign write 1 assign read 1 assign datain 5\h cycle assign write 0 assign read 1 assign datain 6\h cycle sim | End of macro file encountered set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector coladdr COLADDR8 COLADDR7 COLADDR6 COLADDR5 COLADDR4 COLADDR3 COLADDR2 COLADDR1 COLADDR0 radix hex coladdr vector camin PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 radix hex camin vector rowaddr ROWADDR8 ROWADDR7 ROWADDR6 ROWADDR5 ROWADDR4 ROWADDR3 ROWADDR2 ROWADDR1 ROWADDR0 radix hex rowaddr vector camout CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 radix hex camout | Watched Signals and Vectors | | Define your signal and vector watch list here watch camin pad_fst pad_qck busy write watch camout rowaddr coladdr watch wrfifo readfifo empty clk assign pad_qck 0 assign pad_fst 0 assign busy 0 assign camin 0\h cycle assign pad_fst 1 cycle 4 assign pad_fst 0 cycle 4 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 3\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 2\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 1\h cycle 1 assign pad_qck 1 cycle 1 assign busy 1 cycle 2 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 6\h assign pad_qck 0 cycle 3 assign camin 5\h assign pad_qck 1 cycle 3 assign busy 0 assign camin 5\h assign pad_qck 0 cycle 30 sim | End of macro file encountered set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector coladdr COLADDR8 COLADDR7 COLADDR6 COLADDR5 COLADDR4 COLADDR3 COLADDR2 COLADDR1 COLADDR0 radix hex coladdr vector camin PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 radix hex camin vector rowaddr ROWADDR8 ROWADDR7 ROWADDR6 ROWADDR5 ROWADDR4 ROWADDR3 ROWADDR2 ROWADDR1 ROWADDR0 radix hex rowaddr vector camout CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 radix hex camout | Watched Signals and Vectors | | Define your signal and vector watch list here watch camin pad_fst pad_qck busy watch camout rowaddr coladdr write watch wrfifo readfifo empty clk assign pad_qck 0 assign pad_fst 0 assign busy 0 assign camin 0\h cycle assign pad_fst 1 cycle 4 assign pad_fst 0 cycle 4 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 3\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 2\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 1\h cycle 1 assign pad_qck 1 cycle 1 assign busy 1 cycle 2 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 6\h assign pad_qck 0 cycle 3 assign camin 5\h assign pad_qck 1 cycle 3 assign busy 0 assign camin 5\h assign pad_qck 0 cycle 30 sim | End of macro file encountered delete_signals clpr log | Removing existing log file log log | Macro log file Z:\AMMERMAN\CSE567\WORKING\VGACAM\log.log is already opened set_mode functional restart stepsize 10 ns clock clk 0 1 vector coladdr COLADDR8 COLADDR7 COLADDR6 COLADDR5 COLADDR4 COLADDR3 COLADDR2 COLADDR1 COLADDR0 radix hex coladdr vector camin PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 radix hex camin vector rowaddr ROWADDR8 ROWADDR7 ROWADDR6 ROWADDR5 ROWADDR4 ROWADDR3 ROWADDR2 ROWADDR1 ROWADDR0 radix hex rowaddr vector camout CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 radix hex camout watch camin pad_fst pad_qck busy watch camout rowaddr coladdr write watch wrfifo readfifo empty clk h4/wr_cnt0 h4/re_cnt0 assign pad_qck 0 assign pad_fst 0 assign busy 0 assign camin 0\h cycle assign pad_fst 1 cycle 4 assign pad_fst 0 cycle 4 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 3\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 2\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 1\h cycle 1 assign pad_qck 1 cycle 1 assign busy 1 cycle 2 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 6\h assign pad_qck 0 cycle 3 assign camin 5\h assign pad_qck 1 cycle 3 assign busy 0 assign camin 5\h assign pad_qck 0 cycle 30 sim delete_signals clpr log | Removing existing log file log log | Macro log file Z:\AMMERMAN\CSE567\WORKING\VGACAM\log.log is already opened set_mode functional restart stepsize 10 ns clock clk 0 1 vector coladdr COLADDR8 COLADDR7 COLADDR6 COLADDR5 COLADDR4 COLADDR3 COLADDR2 COLADDR1 COLADDR0 radix hex coladdr vector camin PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 radix hex camin vector rowaddr ROWADDR8 ROWADDR7 ROWADDR6 ROWADDR5 ROWADDR4 ROWADDR3 ROWADDR2 ROWADDR1 ROWADDR0 radix hex rowaddr vector camout CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 radix hex camout vector wr_cnt h4/wr_cnt7 h4/wr_cnt6 h4/wr_cnt5 h4/wr_cnt4 h4/wr_cnt3 h4/wr_cnt2 h4/wr_cnt1 h4/wr_cnt0 radix hex wr_cnt vector re_cnt h4/re_cnt7 h4/re_cnt6 h4/re_cnt5 h4/re_cnt4 h4/re_cnt3 h4/re_cnt2 h4/re_cnt1 h4/re_cnt0 radix hex re_cnt watch camin pad_fst pad_qck busy watch camout rowaddr coladdr write watch wrfifo readfifo empty clk wr_cnt re_cnt assign pad_qck 0 assign pad_fst 0 assign busy 0 assign camin 0\h cycle assign pad_fst 1 cycle 4 assign pad_fst 0 cycle 4 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 3\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 2\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 1\h cycle 1 assign pad_qck 1 cycle 1 assign busy 1 cycle 2 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 6\h assign pad_qck 0 cycle 3 assign camin 5\h assign pad_qck 1 cycle 3 assign busy 0 assign camin 5\h assign pad_qck 0 cycle 30 sim set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector coladdr COLADDR8 COLADDR7 COLADDR6 COLADDR5 COLADDR4 COLADDR3 COLADDR2 COLADDR1 COLADDR0 radix hex coladdr vector camin PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 radix hex camin vector rowaddr ROWADDR8 ROWADDR7 ROWADDR6 ROWADDR5 ROWADDR4 ROWADDR3 ROWADDR2 ROWADDR1 ROWADDR0 radix hex rowaddr vector camout CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 radix hex camout vector wr_cnt h4/wr_cnt7 h4/wr_cnt6 h4/wr_cnt5 h4/wr_cnt4 h4/wr_cnt3 h4/wr_cnt2 h4/wr_cnt1 h4/wr_cnt0 radix hex wr_cnt vector re_cnt h4/re_cnt7 h4/re_cnt6 h4/re_cnt5 h4/re_cnt4 h4/re_cnt3 h4/re_cnt2 h4/re_cnt1 h4/re_cnt0 radix hex re_cnt | Watched Signals and Vectors | | Define your signal and vector watch list here watch camin pad_fst pad_qck busy watch camout rowaddr coladdr write watch wrfifo readfifo empty clk wr_cnt re_cnt assign pad_qck 0 assign pad_fst 0 assign busy 0 assign camin 0\h cycle assign pad_fst 1 cycle 4 assign pad_fst 0 cycle 4 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 3\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 2\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 1\h cycle 1 assign pad_qck 1 cycle 1 assign busy 1 cycle 2 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 6\h assign pad_qck 0 cycle 3 assign camin 5\h assign pad_qck 1 cycle 3 assign busy 0 assign camin 5\h assign pad_qck 0 cycle 30 sim | End of macro file encountered set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector coladdr COLADDR8 COLADDR7 COLADDR6 COLADDR5 COLADDR4 COLADDR3 COLADDR2 COLADDR1 COLADDR0 radix hex coladdr vector camin PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 radix hex camin vector rowaddr ROWADDR8 ROWADDR7 ROWADDR6 ROWADDR5 ROWADDR4 ROWADDR3 ROWADDR2 ROWADDR1 ROWADDR0 radix hex rowaddr vector camout CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 radix hex camout vector wr_cnt h4/wr_cnt7 h4/wr_cnt6 h4/wr_cnt5 h4/wr_cnt4 h4/wr_cnt3 h4/wr_cnt2 h4/wr_cnt1 h4/wr_cnt0 radix hex wr_cnt vector re_cnt h4/re_cnt7 h4/re_cnt6 h4/re_cnt5 h4/re_cnt4 h4/re_cnt3 h4/re_cnt2 h4/re_cnt1 h4/re_cnt0 radix hex re_cnt | Watched Signals and Vectors | | Define your signal and vector watch list here watch camin pad_fst pad_qck busy watch camout rowaddr coladdr write watch wrfifo readfifo empty clk wr_cnt re_cnt assign pad_qck 0 assign pad_fst 0 assign busy 0 assign camin 0\h cycle assign pad_fst 1 cycle 4 assign pad_fst 0 cycle 4 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 3\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 2\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 1\h cycle 1 assign pad_qck 1 cycle 1 assign busy 1 cycle 2 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 6\h assign pad_qck 0 cycle 3 assign camin 5\h assign pad_qck 1 cycle 3 assign busy 0 assign camin 5\h assign pad_qck 0 cycle 30 sim | End of macro file encountered set_mode functional restart stepsize 10 ns clock clk 0 1 vector datain datain7 datain6 datain5 datain4 datain3 datain2 datain1 datain0 | Unknown signal or pin name: datain7 - ignored | Unknown signal or pin name: datain6 - ignored | Unknown signal or pin name: datain5 - ignored | Unknown signal or pin name: datain4 - ignored | Unknown signal or pin name: datain3 - ignored | Unknown signal or pin name: datain2 - ignored | Unknown signal or pin name: datain1 - ignored | Unknown signal or pin name: datain0 - ignored radix hex datain | Incorrect signal or pin name: datain vector dataout dataout7 dataout6 dataout5 dataout4 dataout3 dataout2 dataout1 dataout0 | Unknown signal or pin name: dataout7 - ignored | Unknown signal or pin name: dataout6 - ignored | Unknown signal or pin name: dataout5 - ignored | Unknown signal or pin name: dataout4 - ignored | Unknown signal or pin name: dataout3 - ignored | Unknown signal or pin name: dataout2 - ignored | Unknown signal or pin name: dataout1 - ignored | Unknown signal or pin name: dataout0 - ignored radix hex dataout | Incorrect signal or pin name: dataout vector wr_cnt wr_cnt7 wr_cnt6 wr_cnt5 wr_cnt4 wr_cnt3 wr_cnt2 wr_cnt1 wr_cnt0 | Unknown signal or pin name: wr_cnt7 - ignored | Unknown signal or pin name: wr_cnt6 - ignored | Unknown signal or pin name: wr_cnt5 - ignored | Unknown signal or pin name: wr_cnt4 - ignored | Unknown signal or pin name: wr_cnt3 - ignored | Unknown signal or pin name: wr_cnt2 - ignored | Unknown signal or pin name: wr_cnt1 - ignored | Unknown signal or pin name: wr_cnt0 - ignored radix hex wr_cnt | Incorrect signal or pin name: wr_cnt vector re_cnt re_cnt7 re_cnt6 re_cnt5 re_cnt4 re_cnt3 re_cnt2 re_cnt1 re_cnt0 | Unknown signal or pin name: re_cnt7 - ignored | Unknown signal or pin name: re_cnt6 - ignored | Unknown signal or pin name: re_cnt5 - ignored | Unknown signal or pin name: re_cnt4 - ignored | Unknown signal or pin name: re_cnt3 - ignored | Unknown signal or pin name: re_cnt2 - ignored | Unknown signal or pin name: re_cnt1 - ignored | Unknown signal or pin name: re_cnt0 - ignored radix hex re_cnt | Incorrect signal or pin name: re_cnt watch datain dataout clk empty read write reset wr_cnt re_cnt | Incorrect signal or pin name: datain | Incorrect signal or pin name: dataout | Incorrect signal or pin name: empty | Incorrect signal or pin name: read | Incorrect signal or pin name: write | Incorrect signal or pin name: reset | Incorrect signal or pin name: wr_cnt | Incorrect signal or pin name: re_cnt assign reset 0 | Incorrect signal or pin name: reset assign write 0 | Incorrect signal or pin name: write assign read 0 | Incorrect signal or pin name: read assign datain 1\h | Incorrect signal or pin name: datain cycle assign reset 1 | Incorrect signal or pin name: reset assign write 0 | Incorrect signal or pin name: write assign read 0 | Incorrect signal or pin name: read assign datain 1\h | Incorrect signal or pin name: datain cycle assign reset 0 | Incorrect signal or pin name: reset assign write 0 | Incorrect signal or pin name: write assign read 0 | Incorrect signal or pin name: read assign datain 1\h | Incorrect signal or pin name: datain cycle assign write 1 | Incorrect signal or pin name: write assign read 0 | Incorrect signal or pin name: read assign datain 2\h | Incorrect signal or pin name: datain cycle assign write 0 | Incorrect signal or pin name: write assign read 1 | Incorrect signal or pin name: read assign datain 3\h | Incorrect signal or pin name: datain cycle assign write 1 | Incorrect signal or pin name: write assign read 0 | Incorrect signal or pin name: read assign datain 4\h | Incorrect signal or pin name: datain cycle assign write 1 | Incorrect signal or pin name: write assign read 1 | Incorrect signal or pin name: read assign datain 5\h | Incorrect signal or pin name: datain cycle assign write 0 | Incorrect signal or pin name: write set_mode functional restart stepsize 10 ns clock clk 0 1 vector datain datain7 datain6 datain5 datain4 datain3 datain2 datain1 datain0 radix hex datain vector dataout dataout7 dataout6 dataout5 dataout4 dataout3 dataout2 dataout1 dataout0 radix hex dataout vector wr_cnt wr_cnt7 wr_cnt6 wr_cnt5 wr_cnt4 wr_cnt3 wr_cnt2 wr_cnt1 wr_cnt0 radix hex wr_cnt vector re_cnt re_cnt7 re_cnt6 re_cnt5 re_cnt4 re_cnt3 re_cnt2 re_cnt1 re_cnt0 radix hex re_cnt watch datain dataout clk empty read write reset wr_cnt re_cnt assign reset 0 assign write 0 assign read 0 assign datain 1\h cycle assign reset 1 assign write 0 assign read 0 assign datain 1\h cycle assign reset 0 assign write 0 assign read 0 assign datain 1\h cycle assign write 1 assign read 0 assign datain 2\h cycle assign write 0 assign read 1 assign datain 3\h cycle assign write 1 assign read 0 assign datain 4\h cycle assign write 1 assign read 1 assign datain 5\h cycle assign write 0 assign read 1 assign datain 6\h cycle sim set_mode functional restart stepsize 10 ns clock clk 0 1 vector datain datain7 datain6 datain5 datain4 datain3 datain2 datain1 datain0 radix hex datain vector dataout dataout7 dataout6 dataout5 dataout4 dataout3 dataout2 dataout1 dataout0 radix hex dataout vector wr_cnt wr_cnt6 wr_cnt5 wr_cnt4 wr_cnt3 wr_cnt2 wr_cnt1 wr_cnt0 radix hex wr_cnt vector re_cnt re_cnt6 re_cnt5 re_cnt4 re_cnt3 re_cnt2 re_cnt1 re_cnt0 radix hex re_cnt watch datain dataout clk empty read write reset wr_cnt re_cnt assign reset 0 assign write 0 assign read 0 assign datain 1\h cycle assign reset 1 assign write 0 assign read 0 assign datain 1\h cycle assign reset 0 assign write 0 assign read 0 assign datain 1\h cycle assign write 1 assign read 0 assign datain 2\h cycle assign write 0 assign read 1 assign datain 3\h cycle assign write 1 assign read 0 assign datain 4\h cycle assign write 1 assign read 1 assign datain 5\h cycle assign write 0 assign read 1 assign datain 6\h cycle sim set_mode functional restart stepsize 10 ns clock clk 0 1 vector coladdr COLADDR8 COLADDR7 COLADDR6 COLADDR5 COLADDR4 COLADDR3 COLADDR2 COLADDR1 COLADDR0 radix hex coladdr vector camin PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 radix hex camin vector rowaddr ROWADDR8 ROWADDR7 ROWADDR6 ROWADDR5 ROWADDR4 ROWADDR3 ROWADDR2 ROWADDR1 ROWADDR0 radix hex rowaddr vector camout CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 radix hex camout vector wr_cnt h4/wr_cnt7 h4/wr_cnt6 h4/wr_cnt5 h4/wr_cnt4 h4/wr_cnt3 h4/wr_cnt2 h4/wr_cnt1 h4/wr_cnt0 | Unknown signal or pin name: h4/wr_cnt7 - ignored radix hex wr_cnt vector re_cnt h4/re_cnt7 h4/re_cnt6 h4/re_cnt5 h4/re_cnt4 h4/re_cnt3 h4/re_cnt2 h4/re_cnt1 h4/re_cnt0 | Unknown signal or pin name: h4/re_cnt7 - ignored radix hex re_cnt watch camin pad_fst pad_qck busy watch camout rowaddr coladdr write watch wrfifo readfifo empty clk wr_cnt re_cnt assign pad_qck 0 assign pad_fst 0 assign busy 0 assign camin 0\h cycle assign pad_fst 1 cycle 4 assign pad_fst 0 cycle 4 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 3\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 2\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 1\h cycle 1 assign pad_qck 1 cycle 1 assign busy 1 cycle 2 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 6\h assign pad_qck 0 cycle 3 assign camin 5\h assign pad_qck 1 cycle 3 assign busy 0 assign camin 5\h assign pad_qck 0 cycle 30 sim delete_signals clpr log | Removing existing log file log log | Macro log file I:\CSE567\JOHN\WORKING\VGACAM\log.log is already opened set_mode functional restart stepsize 10 ns clock clk 0 1 vector coladdr COLADDR[8:0] radix hex coladdr vector camin PAD_CAM3 PAD_CAM2 PAD_CAM1 PAD_CAM0 radix hex camin vector rowaddr ROWADDR8 ROWADDR7 ROWADDR6 ROWADDR5 ROWADDR4 ROWADDR3 ROWADDR2 ROWADDR1 ROWADDR0 radix hex rowaddr vector camout CAMDATAOUT7 CAMDATAOUT6 CAMDATAOUT5 CAMDATAOUT4 CAMDATAOUT3 CAMDATAOUT2 CAMDATAOUT1 CAMDATAOUT0 radix hex camout vector wr_cnt h4/wr_cnt7 h4/wr_cnt6 h4/wr_cnt5 h4/wr_cnt4 h4/wr_cnt3 h4/wr_cnt2 h4/wr_cnt1 h4/wr_cnt0 | Unknown signal or pin name: h4/wr_cnt7 - ignored radix hex wr_cnt vector re_cnt h4/re_cnt7 h4/re_cnt6 h4/re_cnt5 h4/re_cnt4 h4/re_cnt3 h4/re_cnt2 h4/re_cnt1 h4/re_cnt0 | Unknown signal or pin name: h4/re_cnt7 - ignored radix hex re_cnt watch camin pad_fst pad_qck busy watch camout rowaddr coladdr write watch wrfifo readfifo empty clk wr_cnt re_cnt assign pad_qck 0 assign pad_fst 0 assign busy 0 assign camin 0\h cycle assign pad_fst 1 cycle 4 assign pad_fst 0 cycle 4 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 3\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 2\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 1\h cycle 1 assign pad_qck 1 cycle 1 assign busy 1 cycle 2 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 6\h assign pad_qck 0 cycle 3 assign camin 5\h assign pad_qck 1 cycle 3 assign busy 0 assign camin 5\h assign pad_qck 0 cycle 30 delete_signals clpr log | Removing existing log file log log | Macro log file I:\CSE567\JOHN\WORKING\VGACAM\log.log is already opened set_mode functional restart stepsize 10 ns clock clk 0 1 vector coladdr COLADDR[8:0] radix hex coladdr vector camin PAD_CAM[3:0] radix hex camin vector rowaddr ROWADDR[8:0] radix hex rowaddr vector camout CAMDATAOUT[7:0] radix hex camout vector wr_cnt h4/wr_cnt[6:0] radix hex wr_cnt vector re_cnt h4/re_cnt7 h4/re_cnt6 h4/re_cnt5 h4/re_cnt4 h4/re_cnt3 h4/re_cnt2 h4/re_cnt1 h4/re_cnt0 | Unknown signal or pin name: h4/re_cnt7 - ignored radix hex re_cnt watch camin pad_fst pad_qck busy watch camout rowaddr coladdr write watch wrfifo readfifo empty clk wr_cnt re_cnt assign pad_qck 0 assign pad_fst 0 assign busy 0 assign camin 0\h cycle delete_signals clpr log | Removing existing log file log log | Macro log file I:\CSE567\JOHN\WORKING\VGACAM\log.log is already opened set_mode functional restart stepsize 10 ns clock clk 0 1 vector coladdr COLADDR[8:0] radix hex coladdr vector camin PAD_CAM[3:0] radix hex camin vector rowaddr ROWADDR[8:0] radix hex rowaddr vector camout CAMDATAOUT[7:0] radix hex camout vector wr_cnt h4/wr_cnt[6:0] radix hex wr_cnt vector re_cnt h4/re_cnt[6:0] radix hex re_cnt watch camin pad_fst pad_qck busy watch camout rowaddr coladdr write watch wrfifo readfifo empty clk wr_cnt re_cnt assign pad_qck 0 assign pad_fst 0 assign busy 0 assign camin 0\h cycle assign pad_fst 1 cycle 4 assign pad_fst 0 cycle 4 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 3\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 2\h cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign camin 1\h cycle 1 assign pad_qck 1 cycle 1 assign busy 1 cycle 2 assign camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign camin 6\h assign pad_qck 0 cycle 3 assign camin 5\h assign pad_qck 1 cycle 3 assign busy 0 assign camin 5\h assign pad_qck 0 cycle 30 sim delete_signals clpr log | Removing existing log file log log | Macro log file I:\CSE567\JOHN\WORKING\VGACAM\log.log is already opened set_mode functional restart stepsize 10 ns clock clk 0 1 vector coladdr COLADDR[8:0] radix hex coladdr vector padcamin PAD_CAM[3:0] radix hex padcamin vector rowaddr ROWADDR[8:0] radix hex rowaddr vector camout CAMDATAIN[7:0] radix hex camin | Incorrect signal or pin name: camin vector camout CAMDATAOUT[7:0] | Bus camout already exists radix hex camout vector wr_cnt h4/wr_cnt[6:0] radix hex wr_cnt vector re_cnt h4/re_cnt[6:0] radix hex re_cnt watch padcamin pad_fst pad_qck busy watch camin camout rowaddr coladdr write | Incorrect signal or pin name: camin watch wrfifo readfifo empty clk wr_cnt re_cnt assign pad_qck 0 assign pad_fst 0 assign busy 0 assign camin 0\h | Incorrect signal or pin name: camin cycle assign pad_fst 1 cycle 4 assign pad_fst 0 cycle 4 assign camin 5\h | Incorrect signal or pin name: camin cycle 1 assign pad_qck 1 cycle 3 assign camin 2\h | Incorrect signal or pin name: camin cycle 1 assign pad_qck 0 cycle 3 assign camin 3\h | Incorrect signal or pin name: camin cycle 1 assign pad_qck 1 cycle 3 assign camin 1\h | Incorrect signal or pin name: camin cycle 1 assign pad_qck 0 cycle 3 delete_signals clpr log | Removing existing log file log log | Macro log file I:\CSE567\JOHN\WORKING\VGACAM\log.log is already opened set_mode functional restart stepsize 10 ns clock clk 0 1 vector coladdr COLADDR[8:0] radix hex coladdr vector pad_camin PAD_CAM[3:0] radix hex pad_camin vector rowaddr ROWADDR[8:0] radix hex rowaddr vector camout CAMDATAIN[7:0] radix hex camin | Incorrect signal or pin name: camin vector camout CAMDATAOUT[7:0] | Bus camout already exists radix hex camout vector wr_cnt h4/wr_cnt[6:0] radix hex wr_cnt vector re_cnt h4/re_cnt[6:0] radix hex re_cnt watch padcamin pad_fst pad_qck busy | Incorrect signal or pin name: padcamin watch camin camout rowaddr coladdr write | Incorrect signal or pin name: camin watch wrfifo readfifo empty clk wr_cnt re_cnt assign pad_qck 0 assign pad_fst 0 assign busy 0 assign camin 0\h | Incorrect signal or pin name: camin cycle assign pad_fst 1 cycle 4 assign pad_fst 0 cycle 4 assign pad_camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign pad_camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign pad_camin 3\h cycle 1 assign pad_qck 1 cycle 3 assign pad_camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign pad_camin 2\h cycle 1 assign pad_qck 1 cycle 3 assign pad_camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign pad_camin 1\h cycle 1 assign pad_qck 1 cycle 1 assign busy 1 cycle 2 assign pad_camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign pad_camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign pad_camin 6\h assign pad_qck 0 cycle 3 assign pad_camin 5\h assign pad_qck 1 cycle 3 assign busy 0 assign pad_camin 5\h assign pad_qck 0 cycle 30 sim delete_signals clpr log | Removing existing log file log log | Macro log file I:\CSE567\JOHN\WORKING\VGACAM\log.log is already opened set_mode functional restart stepsize 10 ns clock clk 0 1 vector coladdr COLADDR[8:0] radix hex coladdr vector pad_camin PAD_CAM[3:0] radix hex pad_camin vector rowaddr ROWADDR[8:0] radix hex rowaddr vector camin CAMDATAIN[7:0] radix hex camin vector camout CAMDATAOUT[7:0] radix hex camout vector wr_cnt h4/wr_cnt[6:0] radix hex wr_cnt vector re_cnt h4/re_cnt[6:0] radix hex re_cnt watch pad_camin pad_fst pad_qck busy watch camin camout rowaddr coladdr write watch wrfifo readfifo empty clk wr_cnt re_cnt assign pad_qck 0 assign pad_fst 0 assign busy 0 assign camin 0\h cycle assign pad_fst 1 cycle 4 assign pad_fst 0 cycle 4 assign pad_camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign pad_camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign pad_camin 3\h cycle 1 assign pad_qck 1 cycle 3 assign pad_camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign pad_camin 2\h cycle 1 assign pad_qck 1 cycle 3 assign pad_camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign pad_camin 1\h cycle 1 assign pad_qck 1 cycle 1 assign busy 1 cycle 2 assign pad_camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign pad_camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign pad_camin 6\h assign pad_qck 0 cycle 3 assign pad_camin 5\h assign pad_qck 1 cycle 3 assign busy 0 assign pad_camin 5\h assign pad_qck 0 cycle 30 sim delete_signals clpr log | Removing existing log file log log | Macro log file I:\CSE567\JOHN\WORKING\VGACAM\log.log is already opened set_mode functional restart stepsize 10 ns clock clk 0 1 vector coladdr COLADDR[8:0] radix hex coladdr vector pad_camin PAD_CAM[3:0] radix hex pad_camin vector rowaddr ROWADDR[8:0] radix hex rowaddr vector camin CAMDATAIN[7:0] radix hex camin vector camout CAMDATAOUT[7:0] radix hex camout vector wr_cnt h4/wr_cnt[6:0] radix hex wr_cnt vector re_cnt h4/re_cnt[6:0] radix hex re_cnt watch pad_camin pad_fst pad_qck busy watch camin camout rowaddr coladdr write watch wrfifo readfifo empty clk wr_cnt re_cnt assign pad_qck 0 assign pad_fst 0 assign busy 0 assign pad_camin 0\h cycle assign pad_fst 1 cycle 4 assign pad_fst 0 cycle 4 assign pad_camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign pad_camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign pad_camin 3\h cycle 1 assign pad_qck 1 cycle 3 assign pad_camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign pad_camin 2\h cycle 1 assign pad_qck 1 cycle 3 assign pad_camin 1\h cycle 1 assign pad_qck 0 cycle 3 assign pad_camin 1\h cycle 1 assign pad_qck 1 cycle 1 assign busy 1 cycle 2 assign pad_camin 2\h cycle 1 assign pad_qck 0 cycle 3 assign pad_camin 5\h cycle 1 assign pad_qck 1 cycle 3 assign pad_camin 6\h assign pad_qck 0 cycle 3 assign pad_camin 5\h assign pad_qck 1 cycle 3 assign busy 0 assign pad_camin 5\h assign pad_qck 0 cycle 30 sim delete_signals clpr log | Removing existing log file log log | Macro log file I:\CSE567\JOHN\WORKING\VGACAM\log.log is already opened set_mode functional restart stepsize 10 ns clock clk 0 1 vector coladdr COLADDR[8:0] radix hex coladdr vector pad_camin PAD_CAM[3:0] radix hex pad_camin vector rowaddr ROWADDR[8:0] radix hex rowaddr vector camin CAMDATAIN[7:0] radix hex camin vector camout CAMDATAOUT[7:0] radix hex camout vector wr_cnt h4/wr_cnt[6:0] radix hex wr_cnt vector re_cnt h4/re_cnt[6:0] radix hex re_cnt watch pad_camin pad_fst pad_qck busy watch camin camout rowaddr coladdr write watch wrfifo readfifo empty clk wr_cnt re_cnt assign pad_qck 0 assign pad_fst 0 assign busy 0 assign pad_camin 0\h cycle assign pad_fst 1 cycle 4 assign pad_fst 0 cycle 4 assign pad_camin 5\h cycle 2 assign pad_qck 1 cycle 2 assign pad_camin 2\h cycle 2 assign pad_qck 0 cycle 2 assign pad_camin 3\h cycle 2 assign pad_qck 1 cycle 2 assign pad_camin 1\h cycle 2 assign pad_qck 0 cycle 2 assign pad_camin 2\h cycle 2 assign pad_qck 1 cycle 2 assign pad_camin 1\h cycle 2 assign pad_qck 0 cycle 2 assign pad_camin 1\h cycle 1 assign pad_qck 1 cycle 1 assign busy 1 cycle 2 assign pad_camin 2\h cycle 2 assign pad_qck 0 cycle 2 assign pad_camin 5\h cycle 2 assign pad_qck 1 cycle 2 assign pad_camin 6\h cycle 2 assign pad_qck 0 cycle 2 assign pad_camin 5\h cycle 2 assign pad_qck 1 cycle 2 assign busy 0 assign pad_camin 5\h cycle 2 assign pad_qck 0 cycle 30 sim set_mode functional restart stepsize 10 ns clock clk 0 1 vector coladdr COLADDR[8:0] radix hex coladdr vector pad_camin PAD_CAM[3:0] radix hex pad_camin vector rowaddr ROWADDR[8:0] radix hex rowaddr vector camin CAMDATAIN[7:0] radix hex camin vector camout CAMDATAOUT[7:0] radix hex camout vector wr_cnt h4/wr_cnt[6:0] | Internal counter in FIFO radix hex wr_cnt vector re_cnt h4/re_cnt[6:0] | Internal counter in FIFO radix hex re_cnt watch pad_camin pad_fst pad_qck busy watch camin camout rowaddr coladdr write watch wrfifo readfifo empty clk wr_cnt re_cnt assign pad_qck 0 assign pad_fst 0 assign busy 0 assign pad_camin 0\h cycle assign pad_fst 1 cycle 4 assign pad_fst 0 cycle 4 assign pad_camin 5\h cycle 2 assign pad_qck 1 cycle 2 assign pad_camin 2\h cycle 2 assign pad_qck 0 cycle 2 assign pad_camin 3\h cycle 2 assign pad_qck 1 cycle 2 assign pad_camin 1\h cycle 2 assign pad_qck 0 cycle 2 assign pad_camin 2\h cycle 2 assign pad_qck 1 cycle 2 assign pad_camin 1\h cycle 2 assign pad_qck 0 cycle 2 assign pad_camin 1\h cycle 1 assign pad_qck 1 cycle 1 assign busy 1 cycle 2 assign pad_camin 2\h cycle 2 assign pad_qck 0 cycle 2 assign pad_camin 5\h cycle 2 assign pad_qck 1 cycle 2 assign pad_camin 6\h cycle 2 assign pad_qck 0 cycle 2 assign pad_camin 5\h cycle 2 assign pad_qck 1 cycle 2 assign busy 0 assign pad_camin 5\h cycle 2 assign pad_qck 0 cycle 30 sim set_mode functional restart stepsize 10 ns clock clk 0 1 vector coladdr COLADDR[8:0] radix hex coladdr vector pad_camin PAD_CAM[3:0] radix hex pad_camin vector rowaddr ROWADDR[8:0] radix hex rowaddr vector camin CAMDATAIN[7:0] radix hex camin vector camout CAMDATAOUT[7:0] radix hex camout vector wr_cnt h4/wr_cnt[6:0] | Internal counter in FIFO | Unknown signal or pin name: h4/wr_cnt6 - ignored | Unknown signal or pin name: h4/wr_cnt5 - ignored | Unknown signal or pin name: h4/wr_cnt4 - ignored | Unknown signal or pin name: h4/wr_cnt3 - ignored | Unknown signal or pin name: h4/wr_cnt2 - ignored | Unknown signal or pin name: h4/wr_cnt1 - ignored | Unknown signal or pin name: h4/wr_cnt0 - ignored radix hex wr_cnt | Incorrect signal or pin name: wr_cnt vector re_cnt h4/re_cnt[6:0] | Internal counter in FIFO | Unknown signal or pin name: h4/re_cnt6 - ignored | Unknown signal or pin name: h4/re_cnt5 - ignored | Unknown signal or pin name: h4/re_cnt4 - ignored | Unknown signal or pin name: h4/re_cnt3 - ignored | Unknown signal or pin name: h4/re_cnt2 - ignored | Unknown signal or pin name: h4/re_cnt1 - ignored | Unknown signal or pin name: h4/re_cnt0 - ignored radix hex re_cnt | Incorrect signal or pin name: re_cnt watch pad_camin pad_fst pad_qck busy watch camin camout rowaddr coladdr write watch wrfifo readfifo empty clk wr_cnt re_cnt | Incorrect signal or pin name: wr_cnt | Incorrect signal or pin name: re_cnt assign pad_qck 0 assign pad_fst 0 assign busy 0 assign pad_camin 0\h cycle assign pad_fst 1 cycle 4 assign pad_fst 0 cycle 4 assign pad_camin 5\h cycle 2 assign pad_qck 1 cycle 2 assign pad_camin 2\h cycle 2 assign pad_qck 0 cycle 2 assign pad_camin 3\h cycle 2 assign pad_qck 1 cycle 2 assign pad_camin 1\h cycle 2 assign pad_qck 0 cycle 2 assign pad_camin 2\h cycle 2 assign pad_qck 1 cycle 2 assign pad_camin 1\h cycle 2 assign pad_qck 0 cycle 2 assign pad_camin 1\h cycle 1 assign pad_qck 1 cycle 1 assign busy 1 cycle 2 assign pad_camin 2\h cycle 2 assign pad_qck 0 cycle 2 assign pad_camin 5\h cycle 2 assign pad_qck 1 cycle 2 assign pad_camin 6\h cycle 2 assign pad_qck 0 cycle 2 assign pad_camin 5\h cycle 2 assign pad_qck 1 cycle 2 assign busy 0 assign pad_camin 5\h cycle 2 assign pad_qck 0 cycle 30 sim set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector datain datain7 datain6 datain5 datain4 datain3 datain2 datain1 datain0 radix hex datain vector dataout dataout7 dataout6 dataout5 dataout4 dataout3 dataout2 dataout1 dataout0 radix hex dataout vector wr_cnt wr_cnt6 wr_cnt5 wr_cnt4 wr_cnt3 wr_cnt2 wr_cnt1 wr_cnt0 radix hex wr_cnt vector re_cnt re_cnt6 re_cnt5 re_cnt4 re_cnt3 re_cnt2 re_cnt1 re_cnt0 radix hex re_cnt | Watched Signals and Vectors | | Define your signal and vector watch list here watch datain dataout clk empty read write reset wr_cnt re_cnt assign reset 0 assign write 0 assign read 0 assign datain 1\h cycle assign reset 1 assign write 0 assign read 0 assign datain 1\h cycle assign reset 0 assign write 0 assign read 0 assign datain 1\h cycle assign write 1 assign read 0 assign datain 2\h cycle assign write 0 assign read 1 assign datain 3\h cycle assign write 1 assign read 0 assign datain 4\h cycle assign write 1 assign read 1 assign datain 5\h cycle assign write 0 assign read 1 assign datain 6\h cycle sim | End of macro file encountered | The file has been automatically generated by | the Script Editor File Wizard version 2.0.1.89 | | Copyright | Initial settings delete_signals clpr log | Removing existing log file log log | Macro log file U:\CSE567\JOHN\WORKING\VGACAM\log.log is already opened set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector datain datain7 datain6 datain5 datain4 datain3 datain2 datain1 datain0 radix hex datain vector dataout dataout7 dataout6 dataout5 dataout4 dataout3 dataout2 dataout1 dataout0 radix hex dataout vector wr_cnt wr_cnt6 wr_cnt5 wr_cnt4 wr_cnt3 wr_cnt2 wr_cnt1 wr_cnt0 radix hex wr_cnt vector re_cnt re_cnt6 re_cnt5 re_cnt4 re_cnt3 re_cnt2 re_cnt1 re_cnt0 radix hex re_cnt | Watched Signals and Vectors | | Define your signal and vector watch list here watch datain dataout clk empty read write reset wr_cnt re_cnt assign reset 0 assign write 0 assign read 0 assign datain 1\h cycle assign reset 1 assign write 0 assign read 0 assign datain 1\h cycle assign reset 0 assign write 0 assign read 0 assign datain 1\h cycle assign write 1 assign read 0 assign datain 2\h cycle assign write 0 assign read 1 assign datain 3\h cycle assign write 1 assign read 0 assign datain 4\h cycle assign write 1 assign read 1 assign datain 5\h cycle assign write 0 assign read 1 assign datain 6\h cycle sim | End of macro file encountered set_mode functional restart stepsize 10 ns clock clk 0 1 | Vector Definitions | | Add your vector definition commands here vector coladdr COLADDR[8:0] radix hex coladdr vector pad_camin PAD_CAM[3:0] radix hex pad_camin vector rowaddr ROWADDR[8:0] radix hex rowaddr vector camin CAMDATAIN[7:0] radix hex camin vector camout CAMDATAOUT[7:0] radix hex camout vector wr_cnt h4/wr_cnt[6:0] | Internal counter in FIFO | Unknown signal or pin name: h4/wr_cnt6 - ignored | Unknown signal or pin name: h4/wr_cnt5 - ignored | Unknown signal or pin name: h4/wr_cnt4 - ignored | Unknown signal or pin name: h4/wr_cnt3 - ignored | Unknown signal or pin name: h4/wr_cnt2 - ignored | Unknown signal or pin name: h4/wr_cnt1 - ignored | Unknown signal or pin name: h4/wr_cnt0 - ignored radix hex wr_cnt | Incorrect signal or pin name: wr_cnt vector re_cnt h4/re_cnt[6:0] | Internal counter in FIFO | Unknown signal or pin name: h4/re_cnt6 - ignored | Unknown signal or pin name: h4/re_cnt5 - ignored | Unknown signal or pin name: h4/re_cnt4 - ignored | Unknown signal or pin name: h4/re_cnt3 - ignored | Unknown signal or pin name: h4/re_cnt2 - ignored | Unknown signal or pin name: h4/re_cnt1 - ignored | Unknown signal or pin name: h4/re_cnt0 - ignored radix hex re_cnt | Incorrect signal or pin name: re_cnt | Watched Signals and Vectors | | Define your signal and vector watch list here watch pad_camin pad_fst pad_qck busy watch camin camout rowaddr coladdr write watch wrfifo readfifo empty clk wr_cnt re_cnt | Incorrect signal or pin name: wr_cnt | Incorrect signal or pin name: re_cnt assign pad_qck 0 assign pad_fst 0 assign busy 0 assign pad_camin 0\h cycle | Start with a FST which causes a reset assign pad_fst 1 cycle 4 assign pad_fst 0 cycle 4 | Input 52 assign pad_camin 5\h cycle 2 assign pad_qck 1 cycle 2 assign pad_camin 2\h cycle 2 assign pad_qck 0 cycle 2 | Input 31 assign pad_camin 3\h cycle 2 assign pad_qck 1 cycle 2 assign pad_camin 1\h cycle 2 assign pad_qck 0 cycle 2 | Input 21 assign pad_camin 2\h cycle 2 assign pad_qck 1 cycle 2 assign pad_camin 1\h cycle 2 assign pad_qck 0 cycle 2 | Input 12 assign pad_camin 1\h cycle 1 assign pad_qck 1 | Turn on the memory busy signal cycle 1 assign busy 1 cycle 2 assign pad_camin 2\h cycle 2 assign pad_qck 0 cycle 2 | Input 56 assign pad_camin 5\h cycle 2 assign pad_qck 1 cycle 2 assign pad_camin 6\h cycle 2 assign pad_qck 0 cycle 2 | Input 55 assign pad_camin 5\h cycle 2 assign pad_qck 1 cycle 2 | Turn off the memory busy signal assign busy 0 assign pad_camin 5\h cycle 2 assign pad_qck 0 cycle 30 sim | End of macro file encountered set_mode functional restart stepsize 10 ns clock clk 0 1 vector coladdr COLADDR[8:0] | Unknown signal or pin name: COLADDR8 - ignored radix hex coladdr vector pad_camin PAD_CAM[3:0] radix hex pad_camin vector rowaddr ROWADDR[8:0] | Unknown signal or pin name: ROWADDR8 - ignored radix hex rowaddr vector camin CAMDATAIN[7:0] radix hex camin vector camout CAMDATAOUT[7:0] radix hex camout vector wr_cnt h4/wr_cnt[6:0] | Internal counter in FIFO radix hex wr_cnt vector re_cnt h4/re_cnt[6:0] | Internal counter in FIFO radix hex re_cnt watch pad_camin pad_fst pad_qck busy watch camin camout rowaddr coladdr write watch wrfifo readfifo empty clk wr_cnt re_cnt assign pad_qck 0 assign pad_fst 0 assign busy 0 assign pad_camin 0\h cycle assign pad_fst 1 cycle 4 assign pad_fst 0 cycle 4 assign pad_camin 5\h cycle 2 assign pad_qck 1 cycle 2 assign pad_camin 2\h cycle 2 assign pad_qck 0 cycle 2 assign pad_camin 3\h cycle 2 assign pad_qck 1 cycle 2 assign pad_camin 1\h cycle 2 assign pad_qck 0 cycle 2 assign pad_camin 2\h cycle 2 assign pad_qck 1 cycle 2 assign pad_camin 1\h cycle 2 assign pad_qck 0 cycle 2 assign pad_camin 1\h cycle 1 assign pad_qck 1 cycle 1 assign busy 1 cycle 2 assign pad_camin 2\h cycle 2 assign pad_qck 0 cycle 2 assign pad_camin 5\h cycle 2 assign pad_qck 1 cycle 2 assign pad_camin 6\h cycle 2 assign pad_qck 0 cycle 2 assign pad_camin 5\h cycle 2 assign pad_qck 1 cycle 2 assign busy 0 assign pad_camin 5\h cycle 2 assign pad_qck 0 cycle 30 sim set_mode functional restart stepsize 20 ns clock clk 0 1 vector datain datain7 datain6 datain5 datain4 datain3 datain2 datain1 datain0 radix hex datain vector dataout dataout7 dataout6 dataout5 dataout4 dataout3 dataout2 dataout1 dataout0 radix hex dataout vector wr_cnt wr_cnt6 wr_cnt5 wr_cnt4 wr_cnt3 wr_cnt2 wr_cnt1 wr_cnt0 radix hex wr_cnt vector re_cnt re_cnt6 re_cnt5 re_cnt4 re_cnt3 re_cnt2 re_cnt1 re_cnt0 radix hex re_cnt watch datain dataout clk empty read write reset wr_cnt re_cnt assign reset 0 assign write 0 assign read 0 assign datain 1\h cycle assign reset 1 assign write 0 assign read 0 assign datain 1\h cycle assign reset 0 assign write 0 assign read 0 assign datain 1\h cycle assign write 1 assign read 0 assign datain 2\h cycle assign write 0 assign read 1 assign datain 3\h cycle assign write 1 assign read 0 assign datain 4\h cycle assign write 1 assign read 1 assign datain 5\h cycle assign write 0 assign read 1 assign datain 6\h cycle sim set_mode functional restart stepsize 20 ns clock clk 0 1 | Clock with 40 ns cycle time | Vector Definitions | | Add your vector definition commands here vector pad_camin PAD_CAM[3:0] radix hex pad_camin vector camin CAMDATAIN[7:0] radix hex camin vector camout CAMDATAOUT[7:0] radix hex camout vector rowaddr ROWADDR[7:0] radix hex rowaddr vector coladdr COLADDR[7:0] radix hex coladdr vector wr_cnt h4/wr_cnt[6:0] | Internal counter in FIFO radix hex wr_cnt vector re_cnt h4/re_cnt[6:0] | Internal counter in FIFO radix hex re_cnt | Watched Signals and Vectors | | Define your signal and vector watch list here watch pad_camin pad_fst pad_qck busy watch camin camout rowaddr coladdr write watch wrfifo readfifo empty clk wr_cnt re_cnt assign pad_qck 0 assign pad_fst 0 assign busy 0 assign pad_camin 0\h cycle | Start with a FST which causes a reset assign pad_fst 1 cycle 4 assign pad_fst 0 cycle 4 | Input 52 assign pad_camin 5\h sim 30ns assign pad_qck 1 sim 32ns assign pad_camin 2\h sim 30ns assign pad_qck 0 sim 32ns | Input 31 assign pad_camin 3\h sim 30ns assign pad_qck 1 sim 32ns assign pad_camin 1\h sim 30ns assign pad_qck 0 sim 32ns | Input 21 assign pad_camin 2\h sim 30ns assign pad_qck 1 sim 32ns assign pad_camin 1\h sim 30ns assign pad_qck 0 sim 32ns | Input 12 assign pad_camin 1\h sim 30ns assign pad_qck 1 sim 32ns assign pad_camin 2\h sim 30ns assign pad_qck 0 sim 32ns | Turn on the memory busy signal assign busy 1 | Input 56 assign pad_camin 5\h sim 30ns assign pad_qck 1 sim 32ns assign pad_camin 6\h sim 30ns assign pad_qck 0 sim 32ns | Input 55 assign pad_camin 5\h sim 30ns assign pad_qck 1 sim 32ns | Turn off the memory busy signal assign busy 0 assign pad_camin 5\h sim 30ns assign pad_qck 0 sim 1000 | End of macro file encountered