# Xilinx CORE Generator 2.1i
# User = ammerman
SETPROJECT Z:\ammerman\cse567\start\vgacam
# busformat=BusFormatNoDelimiter
# designflow=Schematic
# expandedprojectpath=Z:\ammerman\cse567\start\vgacam
# flowvendor=Viewlogic
# simulationoutputproducts=None
# xilinxfamily=XC4000
# expandedprojectpath=Z:\ammerman\cse567\start\vgacam
# Set current Project to Z:\ammerman\cse567\start\vgacam
# Xilinx CORE Generator
SET FoundationPath = D:\Fndtn
SET XilinxFamily = XC4000
SET BusFormat = BusFormatAngleBracket
SET DesignFlow = Schematic
SET FlowVendor = Foundation
SET SimulationOutputProducts = VHDL Verilog
SET OverwriteFiles=True
#SET LockProjectProps = true
SELECT Synchronous_FIFO XC4000 Xilinx 1.0
SELECT Synchronous_FIFO XC4000 Xilinx 1.0
CSET Dual_Port = TRUE
CSET Data_Width = 8
CSET FIFO_Depth = 160
CSET Component_Name = dfifo160
GENERATE
# Successfully generated dfifo160 (Synchronous_FIFO 1.0)
END