r#CoreGen Instantiations
##dfifo160#CoreGen Instantiations
----------------------------------------------------------------------
-- This file was created by the Xilinx CORE Generator tool, and     --
-- is (c) Xilinx, Inc. 1998, 1999. No part of this file may be      --
-- transmitted to any third party (other than intended by Xilinx)   --
-- or used without a Xilinx programmable or hardwire device without --
-- Xilinx's prior written permission.                               --
----------------------------------------------------------------------

-- The following code must appear in the VHDL architecture header:

------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component dfifo160
	port (
	d: IN std_logic_VECTOR(7 downto 0);
	we: IN std_logic;
	re: IN std_logic;
	reset: IN std_logic;
	c: IN std_logic;
	full: OUT std_logic;
	empty: OUT std_logic;
	bufctr_ce: OUT std_logic;
	bufctr_updn: OUT std_logic;
	q: OUT std_logic_VECTOR(7 downto 0));
end component;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------

-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.

------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : dfifo160
		port map (
			d => d,
			we => we,
			re => re,
			reset => reset,
			c => c,
			full => full,
			empty => empty,
			bufctr_ce => bufctr_ce,
			bufctr_updn => bufctr_updn,
			q => q);
-- INST_TAG_END ------ End INSTANTIATION Template ------------

-- The following code must appear above the VHDL configuration
-- declaration. An example is given at the end of this file.

------------- Begin Cut here for LIBRARY Declaration -------- LIB_TAG

-- synopsys translate_off

Library XilinxCoreLib;

-- synopsys translate_on

-- LIB_TAG_END ------- End LIBRARY Declaration ------------

-- The following code must appear within the VHDL top-level
-- configuration declaration. Ensure that the translate_off/on
-- compiler directives are correct for your synthesis tool(s).

------------- Begin Cut here for CONFIGURATION snippet ------ CONF_TAG

-- synopsys translate_off

	for all : dfifo160 use entity XilinxCoreLib.fifosyncVHT(behavioral)
		generic map(
			Depth => 160,
			Create_RLOCs_for_TBUFs => 0,
			Dual_Port => 1,
			Port_Width => 8,
			Address_Width => 8);
	end for;

-- synopsys translate_on

-- CONF_TAG_END ------ End CONFIGURATION snippet ------------

-------------------------------------------------------------
-- Example of configuration declaration...
-------------------------------------------------------------
--
-- <Insert LIBRARY Declaration here>
--
-- configuration <cfg_my_design> of <my_design> is
--     for <my_arch_name>
--         <Insert CONFIGURATION Declaration here>
--     end for;
-- end <cfg_my_design>;
--
-- If this is not the top-level design then in the next level up, the following text
-- should appear at the end of that file:
--
-- configuration <cfg> of <next_level> is
--     for <arch_name>
--           for all : <my_design> use configuration <cfg_my_design>;
--           end for;
--     end for;
-- end <cfg>;
--
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