// This module takes pixel values from the FIFO and writes the top left 
// 256x256 pixels into the VGA memory space. We throw away the pixels
// outside this 256x256 area
// Memory asserts BUSY when it can't do the write - we repeat the write
// until BUSY is not asserted

module camera_test (Clk, Empty, Fst, Busy, addr_low, addr_high, Write, RE, frameEnd);

input Clk ;
input Empty ;
input Fst ;    			// frame start signal from the camera
input Busy ;   			// busy signal from memory
output [7:0] addr_low ;	// address to memory
output [7:0] addr_high;
output Write ;			// write signal to memory
output RE ;				// Read signal to FIFO - move to the next entry

reg [8:0] hcnt, next_hcnt;		//horizontal pixel counter
reg [8:0] vcnt, next_vcnt;		//vertical line counter
reg Write, RE;
parameter LINESIZE = 351;	// Length of a line from the camera

assign addr_low = {hcnt[7:0]};
assign addr_high = {vcnt[7:0]};

wire inImage;
assign inImage =  hcnt < 256 && vcnt < 256;

assign frameEnd = (vcnt == 256);	// End of frame when we get to the 256th row
always @ (posedge Clk) begin
  if (Fst) begin		// We reset everything on Fst
     hcnt <= 0;
     vcnt <= 0;
  end else begin
     hcnt <= next_hcnt;
     vcnt <= next_vcnt;
  end
end

always @ (hcnt or vcnt or inImage or Fst or Busy or Empty) begin
    Write = 0;			// Default values
    RE = 0;
    next_hcnt = hcnt;
    next_vcnt = vcnt;

    if (!Fst) begin // frame reset signal
    
// If the FIFO has something, and we are in the image, write to memory
	    if(!Empty && inImage) Write = 1;
	    
// If we had a pixel and memory was not busy, or we were not in the image, go on to next pixel
      	if (!Empty && (!Busy || !(inImage))) begin
 	    	RE = 1;
 	    	next_hcnt = hcnt + 1;
			if(hcnt >= LINESIZE) begin	// if we are at the end of the line
		  		next_hcnt = 0;			// on to next row
    			next_vcnt = vcnt + 1;
			end
	   end
   end
end

endmodule