Table of Contents
Register renaming (1)
Register renaming (2)
More on reorder buffer
Example machine
Multiple issue alternatives
Multiple issue for dynamic scheduling
Impact of superscalar on IF
The decode stage (simple case: dual issue and static scheduling)
Instruction commit step
An instruction goes through 4 stages
Execute (like Tomasulo)
VLIW
Limits to ILP
Hardware techniques to enhance ILP
Predication
Conditional Moves
Instruction nullification (in HP PA)
General speculative execution
What limits ILP: Short basic blocks + data dependencies
What limits ILP: hardware complexity
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Author: cselab
Email: baer@cs
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