When & where

Instructor

TA

Course Material

The purpose of this course is to give you a good understanding of how pipelined processors work, both on the conceptual and implementational levels. We'll begin by learning the basics of pipelining (its purpose, its components, pipeline hazards), examine how instructions flow through the pipeline, including the situations in which they get stalled or flushed, and end up knowing how pipelines are constructed in current high-performance processors. Our practical experience will be a Verilog implementation of one of the original RISC pipelines, the MIPS R2000. You must have already taken 370 and 378 in order to take this class.

Reading

All reading assignments will taken from Computer Organization & Design: the Hardware/Software Interface by David A. Patterson and John L. Hennessy, Morgan Kaufmann, 1998. To get the most out of the lectures, try to read the material before topics are discussed in class. Begin by reviewing some material you studied for 378, Chapter 5. We won't be covering the material in class explicitly, but it is important background for understanding the pipelining material. (Alternatively, if you feel confident that you remember the 378 material, you could read the sections of Chapter 5 that are referenced in Chapter 6, as you are reading Chapter 6.)

The Verilog reference manual assumes you already know Verilog. If you need a quick refresher or if you have never used Verilog, take a look at the Verilog tutorial at http://www.eg.bucknell.edu/~cs320/1995-fall/verilog-manual.html. In the second week of the course Jonathan will give several lectures on Verilog, first explaining its constructs and how you use them, then covering some of the key issues in Verilog usage, such as expressing parallel operations and controlling time. For the lectures on today's pipelined processors, I will pass out articles from Microprocessor Report which discuss the implementations.

Exams

There will be a midterm and a final. The final will cover material from the entire course, but will be heavily biased toward what we discuss after the midterm.

Project

The project is to implement in Verilog the pipeline of the MIPS R2000/R3000 processor. The purpose of the project is to give you sound, practical experience in designing and implementing a pipeline, and in expressing that implementation in a widely-used hardware description language. When doing the project, you should use the Patterson & Hennessy text as a guide as to what the hardware should do, and then you make the leap to realize it in your implementation. This "leap" is the important part of the project: it is what will teach you to make good hardware design decisions. The first few assignments will contribute to and prepare you for the main part of the project by giving you practice is writing and simulating Verilog hardware descriptions on small components of a processor. You should team up with one other person to do the project. Some of you already know Verilog, some of you do not. I'm hoping that each team will consist of one person from each group. Send Jonathan email with the names and email addresses of the people on your team this week. All homework is due at the beginning of class; no late assignments will be accepted.

Machines

We'll be using a several Suns for the project: the LIS Suns (omak, lutefisk, manastash chelan puyallup bergen hammahamma nooksack) before Nov. 1, and additional UltraSparcs (chiwawa elwha rhodes tolt) afterwards. All can be accessed from the instructional labs. These machines have been loaned to us by two research groups, who will continue to use them for their research projects with. So try to be good citizens with respect to computer time.

Grading

Grades will be computed using the following approximate weighting: midterm = 25%, final = 35% (or maybe 30%/30% if they are both midterms) and project = 40%. Class participation counts.

Collaboration

Discussing the course content with fellow students is an effective way to learn the material, and is encouraged. However, exams must represent your own mastery of the material, and projects must represent the contribution of your team.

Communicating

We will communicate a lot through e-mail. Jonathan and I will be mailing out assignments and clarifications of the assignments, if needed. And you should use e-mail for asking and answering each others' questions. (But if you have questions that need a detailed or long explanation, it would be much easier to come to our office hours.) Therefore you should register on the class mailing list immediately.