CSE 471 - Tentative and Developing Course Outline

week	Monday	Wednesday	Friday
9/29	Administration Execution cycle review Chapter 5	Pipelining basics read Chapter 6, sections 6.1-6.3	Pipelining basics Structural Hazards
10/6	Verilog read the Verilog tutorial	Verilog	Verilog read Chapter 6, sections 6.4-6.5
10/13	Data hazards	Finish data hazards Control hazards read Chapter 6, section 6.6	More control hazards read the branch prediction handout
10/20	Control hazards basic Verilog assignment due	Branch Target Buffer *read Chapter 6, section 6.7*	Superscalars read Chapter 6, section 6.8
10/27	Dynamic scheduling Review for midterm ALU assignment due	Today's pipelines read Chapter 6, sections 6.9-6.12	Today's pipelines
11/3	Midterm	R2000 pipeline framework read the Verilog code for the pipeline infrastructure	R2000 pipeline framework
11/10	R2000 pipeline framework	R2000 pipeline framework	midterm solution discussion BTB assignment due
11/17	Review of caching and address translation read Chapter 7, selected sections (exact sections sent in email)	Review of caching and address translation	Advanced cache topics TBL part of last assignment should be done
11/24	Advanced cache topics Today's cache hierarchires	Multiprocessors	No class: Thanksgiving holiday
12/1	Multiprocessors read Chapter 9.1-9.5	Cache Coherency	Cache Coherency
12/8	Synchronization Today's MPs Review for final	Multiprocessors pipeline assignment due	Final: 8:30am

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Last updated: 12/5/97