1. The trend is that R+M machine tends to have more percentage of branch instructions while L/S machines tend to have the lowest percentage of branch instructions. The reason is that for every computation task there exists a fixed number of branches but the encoding for different kinds of machines differs. Because R+M has the most compact encoding, it has the highest percentage of branches.
2. L/S machine:
LD.W R1, B
LD.W R2, C
ADD.2 R3, R2, R1
ST.W A, R3
(4 words)
R/M machine:
LD.W R1, B
ADD.2 R1, C
ST.W A, R1
(3 words)
R+M machin:
ADD.W A, B, C
( 2 words)
3. Page 151, we get 6.9 instructions gain using the perfect register window. So in all, the total execution speed up is 110.9/104 - 1 = 6.6%
4. system call/return: 84*1.5/12 = 10.5
trap/interrupt: 103*1.5 / 14 = 11.0
page table entry change: 36*1.5 / 11 = 4.0
context switch: 135 * 1.5 / 9 = 22.5
5. Basically, instruction run-length is the number of instructions between branches.
One would expect L/S machines to have a larger run-length simply it has the lowest percentage of branch intructions. (refer to Question 1)
6. BC, BR, BCR, BRR 0.524 * (0.2 + 0.432)
+ loop control 0.071 * 0.91
+ procedure call 0.405
-----------------------
total = 0.8
7. The centered branch table contains both prefetched instructions and retained preciously executed instructions.
64 words (256 bytes) would be needed for an L/S architecture to be at least 50% effective. (refer to figure 3.12)
8. 58.557% of instructions in a program depends for their execution on data values computed in the previous three instructions.
0.586 * 0. 53 = 0.31 cycles.
9. IF/IF/D/EX/MEM/MEM/WB
10. ADD: IF/IF/D/EX /MEM/MEM/WB
BC: BLANK/IF/IF/D/EX/MEM/MEM/WB
TARGET: BLANK/BLANK/IF/IF/BLANK/TIF/TIF/D
INLINE: BLANK/BLANK/IF/IF/BLANK/D
11. ADD: IF/IF/D/EX/MEM/MEM/WB
ADD: BLANK/IF/IF/D/BLANK/BLANK/EX/MEM/MEM/WB
12. for question 10, we have 1.5 cycles delay( 1 or 2) and for question 11, we have 2 cycles delay.
13. The previous AG instruction is waiting for the result of the former instruction. The AG is controlled by the output of the decocde, so a new decode can't be stored until AG is finished.
14. Because compilers could make use of it to reorganize the instructions so that decoding pipeline delay can be reduced and free instructinons could be executed.
15. A Run-on instruction is basically an instruction that occupies the execution unit for many cycles than for basic instructions.
e.g., multiply or divide unit.