General Information
Meets: MWF 10:30-11:20, Loew 106
Instructor: Ted Kehl
Office Hours: Wednesday 2-3, Thursday 11.30-12.30
E-mail address: ted@cs
Office: Sieg 211 543-2421
TA: Meng-Hee Heng
Office Hour: Mon 3.00-4.30, Thur 1.30-3.00 Sieg 326A
E-mail address: menghee@cs
Catalog Description
CPU instruction addressing models, CPU structure and functions,
computer arithmetic and logic unit, register transfer level design,
hardware and microprogram control, memory hierarchy design and
organization, I/O and system components interconnection. Laboratory
project involves design and simulation of an instruction set
processor.
Prerequisite: CSE 370 and CSE 378.
Class notes
Day 1 (Postscript)
Day 2 (Postscript)
Day 4 (Postscript)
Day 5 (Postscript)
Day 6 (Postscript)
Day 8 (Postscript)
Day 9 (Postscript)
Day 10 (Postscript)
Day 13 (Postscript)
Day 16 (Postscript)
Day 19 (Postscript)
Day 25 (Postscript)
Day 30 (Postscript)
Previous Quarters
Verilog reference card.
Meng-Hee Heng
menghee@cs.washington.edu