General Information
Meets: MWF 10:30-11:20, Loew 102
Instructor: Larry Snyder
Office Hours: MW 4:30-5:30 or by appointment.
E-mail address: snyder@cs
Office: Sieg 426B 543-9265
Assistant: Judy Watson (jwatson@cs), Sieg 426E, 543-0374.
TA: Robert Chen
Office Hours: Sieg 326A, 4:30-5:30 Tuesdays/Thursdays
E-mail address: chensg@cs
Catalog Description
CPU instruction addressing models, CPU structure and functions,
computer arithmetic and logic unit, register transfer level design,
hardware and microprogram control, memory hierarchy design and
organization, I/O and system components interconnection. Laboratory
project involves design and simulation of an instruction set
processor.
Prerequisite: CSE 370 and CSE 378.
Class notes
Monday, 30 Sep 96 (Postscript) Reading: 1.1-1.4
Wednesday, 2 Oct 96 (Postscript) Reading: 1.5-1.6
Friday, 4 Oct 96 (Postscript) Reading: 1.7-1.10
Monday, 7 Oct 96 (Postscript),
Review Sheet and
Answer Sheet.
Wednesday, 9 Oct 96 (Postscript)
Friday, 11 Oct 96 (Postscript)
Monday, 14 Oct 96 (Postscript),
Homework 1,
ALU in HTML, Reading: Skim Appendix A
Wednesday, 16 Oct 96 (Postscript)
Friday, 18 Oct 96 (Color Postscript), Reading: 3.1-3.2
Monday, 21 Oct 96 (Postscript), Reading: 3.3-3.4
Wednesday, 23 Oct 96 (Postscript),
Homework 2, Reading: 4.1-4.2
Friday, 25 Oct 96 (Postscript), Reading: 4.3.1-2
Monday, 28 Oct 96 (Postscript),
Homework 3, Reading: Skim H&P, Chap 6.
Wednesday, 30 Oct 96 (Postscript)
Friday, 1 Nov 96 (Postscript)
Monday, 4 Nov 96 (Revised),
Review
Wednesday, 6 Nov 96 (Postscript),
Review Answers
Friday, 8 Nov 96 Midterm Fast Answers
Holiday Monday, 11 Nov 96
Wednesday, 13 Nov 96 (Postscript),
Homework 4, Reading: 4.6
Friday, 15 Nov 96 (Postscript)
Monday, 18 Nov 96 (Postscript)
Wednesday, 20 Nov 96 (Postscript),
Homework 5,6,7
Friday, 22 Nov 96 (Postscript), Reading: 2.3
Monday, 25 Nov 96 Q&A on Lab Assignment
Wednesday, 27 Nov 96 Chalk-talk on Chaos Routing
Holiday Friday, 29 Nov 96
Monday, 2 Dec 96 (Postscript), Reading: 5.1-5.5
Wednesday, 4 Dec 96 (Postscript), Reading: 5.6,5.7
Friday, 6 Dec 96 (Postscript), Reading: 5.10-5.12, 5.16-5.17
Monday, 9 Dec 96, Video of Colwell P6 lecture,
Review Sheetand answer sheet
Wednesday, 11 Dec 96 (Postscript)
Lab Materials
The following files are available for the Verilog pipeline design:
Verilog simulation of MIPS pipeline, pipeline.v.
Additional modules for pipeline design, common.v.
Sample program, source form, test.s.
Sample program, program segment in "binary", prog.bin.
Sample program, data segment in "binary", data.bin.
Simple assembler for MIPS assembly language, asm.bin.
Man page for the assembler, man.
Previous Quarters
Fall 95
Fall 94
Verilog References
This is a free Postscript
Verilog reference card.
TA
TA@cs.washington.edu