10/4
10/3
10/2
10/1
Date Posted | Date Due | Number | PS | Sample solutions | |
---|---|---|---|---|---|
10/3 | 10/10 | 1 | X | X | Simplescalar configuration file, answers to questions |
10/11 | 10/24 | 2 | X | X | |
10/24 | 11/2 | 3 | X | X | Answers |
11/4 | 11/21 | 4 | X | X | |
11/21 | 12/5 | 5 | X | X | |
12/5 | 12/12 | 6 | X | X |
Date | Topic | PPT | |
---|---|---|---|
10/1 | Review 1 | X | X |
10/5 | Branch Prediction | X | X |
10/17 | Exceptions | X | X |
10/22 | Multiple pipes | X | X |
10/22 | ILP | X | X |
10/24 | Dynamic Scheduling | X | X |
10/26 | Renaming | X | X |
10/29 | Mulitple Instruction Issue | X | X |
11/2 | VLIW | X | X |
11/5 | Multithreading | X | X |
11/9 | Cache Intro | X | X |
11/16 | Cache Performance | X | X |
11/21 | Main Memory | X | X |
11/26 | Memory Hierarchy | X | X |
11/28 | Virtual Memory | X | X |
11/30 | Multiprocessors | X | X |
12/4 | Snoopy Protocols | X | X |
12/5 | NUMA | X | X |
12/7 | Directory Protocols | X | X |
12/12 | Synchronization | X | X |
Date | Topic | PS | HTML | |
---|---|---|---|---|
10/1 | Introduction | X | X | |
10/1 | Outline | X | X | |
10/4 | Using SimpleScalar Simulator at UW | X | ||
10/11 | Report guideline | X | X | |
10/29 | Midterm Winter 2000 | X | X | |
10/29 | Final Winter 2000 | X | X | |
11/9 | Midterm Autumn 2001 answers | X | X |
Name | Office | Office Hours | |
---|---|---|---|
Professor Jean-Loup Baer | baer@cs.washington.edu | 211 Sieg Hall | M 1:30-2:30 F 2:30-3:30 or by appointment |
Name | Office Hours Location | Office Hours | |
---|---|---|---|
Douglas Low | douglas@cs.washington.edu | Sieg 226a / 2nd floor Sieg corridor |
Tu 1:30-2:30 Sieg 226a, Th 1:30-2:30 2nd floor Sieg corridor |
Days | Time | Place |
---|---|---|
MWF | 10:30 - 11:20 | MEB 248 |
Days | Time | Place |
---|---|---|
Th | 10:30 - 11:20 | MEB 248 |
PS | ||
---|---|---|
J.Smith "Characterizing Computer Performance with a Single
Number" CACM vol 31, 10, Oct 1988 pp 1202-1206 |
X | X |
T-S. Yeh and Y.Patt "A Comparison of Dynamic Branch Prediction that
use Two Levels of Branch History" Proc. 20th Int. Symp. Computer Architecture, 1993, pp 257-266 |
X | X |
J.Smith and G. Sohi "The Architecture of Superscalar Microprocessors" Proc. IEEE, 83,12, Dec 1995 |
X | X |
M.Schlansker and B. Rau "EPIC: Explicitly Parallel Instruction Computing" Computer, Feb 2000, 37-45 |
X | X |