CSE469: COMPUTER ARCH I
Instruction: Mark Oskin
TAs: Doruk Arisoy (arisod@uw.edu)
Trung Le (tle45@uw.edu)
Qihuang Chen (cqh99@uw.edu)
Aditya Kumar (adikumar@uw.edu)
Office hours by appointment. Email, text or message the course staff on Slack to setup a time.
Announcements
WEEK 1
- Monday (01/04) - Class on Zoom! Link and recording on Canvas.
- Tuesday (01/05) - Slack channel invite link posted on Canvas.
- Wednesday (01/06) - HW 1 posted
WEEK 2
- Monday (01/11) - Our RISC-V 32-bit simulator bug is fixed and updated.
- Wednesday (01/13) - Recommended reading: 1.1–1.4, 2.1–2.8, 2.14
- Friday (01/15) - HW 1 deadline extended to Jan 20th.
WEEK 3
WEEK 4
- Monday (01/25) - HW 2 posted.
- Wednesday (01/27) - Lab 1 posted.
WEEK 5
- Wednesday (02/03) - Midterm will be soon (more info to come)
WEEK 6
- Monday (02/08) - HW 3 posted.
- Monday (02/08) - See Canvas announcements to signup for a lab demo
WEEK 7
- Monday (02/15) - Recommended reading: Lab 1: 4.1-4.5 Lab 2: 4.6-4.9
- Monday (02/15) - Lab 1 demo slots extended, see Canvas announcements
- Thursday (02/18) - Lab 2 posted.
Materials
Assignments
Lab 2: Due Mar 5
Homework 3: Due Mar 5
Lab 1: Due Feb 10
Homework 2: Due Feb 3
Homework 1: Due Jan 20
RISC-V Dev tools
RISC-V Environment Setup Guide
RISC-V GNU Toolchain (Compiler, assembler, linker, etc.)
Our RISC-V 32-bit simulator
Our RISC-V 32-bit simulator (Mac version)
Cornell Online RISC-V Simulator (Good for visualization but limited instructions)
RISC-V ISA Spec
Verilog info
Scott Hauck's Verilog tutorial
Michael Taylor's Verilog tutorial
Textbook
Computer Architecture: A Quantitative Approach by: David A Patterson and John L. Hennessy (RISC-V Edition)