CSE467: Advanced Logic Design

Carl Ebeling, Winter 1999


Hardware Laboratory - Overview and Policies

Lab assignments will be completed in the Digital Design Laboratory (327 Sieg). (You may also use the workstations in the 232 Pentium lab after the design tools are installed.) There are 10 Intel Pentium workstation on workbenches in the lab. There are also a number of other PCs and Macs which we will not be using much, if at all. The logic analyzers and digital oscilloscopes you will be using are at approximately one half of the benches. In addition, there also is a DataI/O PLD and microcontroller programmer. Multi-meters, oscilloscopes, and other tools and equipment are available. The hardware lab Web Page contains general information and policies as well as a list of the parts currently available for projects. Please read this page carefully!

Laboratory Hours:

CSE467 A: Monday 2:30-5:20
CSE467 B: Wednesday 2:30-5:20

Since 467 is sharing the hardware lab with 477, you cannot leave your projects on a lab bench for a long time.  If you do have to leave for a short time and there is noone waiting to use a bench, leave a note saying who you are.  If you are leaving for very long at all, then put away your project so someone else can use the bench.  We will try to provide each group with a locking drawer to store their project.  However, there is a 2 hour time limit to using a bench if there are students waiting.

Computer-Aided Design Software (Xilinx Foundation): This course will make heavy use of CAD software in the form of
some new Xilinx and Synopsys FPGA tools. These tools will allow us to design using a mixture of schematics and Verilog, using libraries of components for schematics and synthesis tools for Verilog.  The Xilinx Foundation tools include a simulator that will allow us to verify our designs before placing and routing.  These tools are installed on the 327 PCs as well as the PCs in the undergrad NT labs.  Unless you are actively downloading and testing designs onto the XESS boards, we strongly suggest you use the general PCs.

Design Kits: Design Kits are portable kits that contain everything needed to complete the laboratory assignments.  As part of your Design Kit, you will be given (or have access to) an XESS board which contains a Xilinx 4010XL FPGA, a 32Kx8 static RAM and an interface to the PC.  Project teams will check out DesignKits for the quarter (kits will be available the second week of the quarter). In the DesignKit will be a card for keeping track of extra items that you may need to check out during the quarter. You will give us a $200 security deposit for the DesignKit and XESS boards in the form of a check that will be returned to you at the end of the quarter.

Money: You will need to bring a check to your lab section which will be used for a $200 security deposit for each the DesignKits you are issued and other materials, parts, tools, equipment, and documentation you may check out from the lab. Make checks out to the "University of Washington". The $200 checks will be returned at the end of the quarter when the DesignKits and any other parts, equipment, or documentation borrowed in the interim are returned in good shape. You will be held personally responsible for any damage to parts and equipment.


ebeling@cs.washington.edu