You should work on this lab in teams of two. Remember that you both of you will be responsible for knowing how to do everything even if you don't do everything. Your partner next week will probably not be the same partner as this week.
Simulate your design first to make sure it works OK. The following section will describe how to connect your circuit to the appropriate Xilinx chip pads so that you can implement and test it on the XESS board.
Once you have designed and simulated your circuit, you are ready to add the elements necessary for implementing it on the XESS board. In particular you need to add the following symbols:
To use use this UCF in your project (instead of the default one Xilinx creates), first copy it to your project directory. Then go into the Project Manager, select Implementation -> Implementation Options, and choose this constraint file. You can edit the UCF file by double-clicking on it in the Project Manager. To modify our example UCF for your own use, just un-comment the lines that pertain to your design, and add any additional pin mappings that you require. In addition, you need some way to tell Xilinx which PAD/BUF in your schematic corresponds to which net name in your UCF. To do this, simply name the wire between the desired BUF and PAD (in your schematic), giving it the exact same name (case-sensitive!) as the corresponding net name in the UCF. Note, however, that bus names can be given as either X[2] or X<2> in the UCF file.
The UCF contains lines for the pins connected to the 7-segment display. Use these pins to connect the 7 outputs of your circuit. Then add two lines for the data input and reset inputs for your circuit and assign them to pin 27 and pin 28.
We should point out that there's an alternative way of specifying pin mappings which you may wish to use. To do this, your first double-click on an IPAD or OPAD in the schematic to bring up its Symbol Properties dialog box. Under Parameters, enter LOC for the name, and Pxx for the Description (where xx is a pin number, from 0 to approximately 84). Then click on Add, and close the window. This can be convenient for user-definable pin locations, but for signals that need to be mapped to specific pins on the XESS board, using the UCF is probably much safer.
At this point, it's possible you will get warnings or errors that will need to be looked at very carefully. To view the report file, select the Reports tab from the Project Manager screen, and then double-click on Implementation Report Files. If you get any errors, check the implementation report; you most likely just need to go back and tweak some things related to the I/O BUFs and PADs, or perhaps the pin assignments in the UCF.
The implementation phase, once successful, will create a bitstram (.bit) file in your project directory. (Note: if you need an older .bit file, it will be located in a \verXX\revXX subdirectory, since Xilinx automatically creates a new version and/or revision each time you complete the implement phase. The current version of your project can be found by looking on the Project Manager screen, right above the Design Entry button.)
Once you have the bitstream file you can download it to the XESS board using the 'xsload' program (located in 'c:\xstools\bin\'). This program downloads a bitstream onto the XESS board through a parallel-port cable that you plug into the PCs. To use it, simply connect the XESS board to your PC via the parallel cable, and plug-in the XESS board's power cord. Then run the xsload program from the Windows command prompt, giving it the name of your .bit file as an argument. That's all there is to it! Please note that the PCs in the lab are the only ones that have the xsload software installed, so you should not remove the parallel cables or the XESS boards from the lab.
PLEASE READ THE INSTRUCTIONS on using the protoboard is contained in the Design Kit web page. For this lab, you should pay particular attention to the section on switches.
Repeat this process with the second push-button switch so that you now have two switches connected up. The next step is to connect these two switches to the inputs of your circuit in the Xilinx chip. This means that you will need to connect the XESS board to the protoboard. When you do this, you will use one power supply for the protoboard and another power supply for the XESS board. To make this work without ruining things, you MUST CONNECT THE GROUNDS OF THE TWO BOARDS.
First disconnect all power supplies from the protoboard and the XESS board. The XESS board should be already be inserted into a couple protoboards to make it easy to connect to pins of the XESS board, which are connected to the Xilinx chip pins. The pins of the XESS board are numbered from 1 to 84, counter-clockwise around the board, starting in the center of the left-hand side of the board, down to the bottom pin (pin 21) then up the right-hand side of the board from pin 22 to 63, then down the left-hand side of the board from pin 63 to 84.
IMPORTANT: Connect pin 52 (GND) of the XESS board to a GND bus on the Design Kit protoboard. Before you plug power into the XESS board, doublecheck to make sure that you have the GND signals connected correctly. Use the multimeter to measure the resistance between the grounds on the two boards - it should be 0. Also measure the resistance between Vdd and GND on the two boards - it should be very high (e.g. high enough not to register).
Next connect the two switches to pins 27 and 28 of the XESS board, which are connected to pins 27 and 28 of the Xilinx chip.
Now plug power into the XESS board and download and try out your circuit. Each press of the switch should give you a random number of counts because of the bouncing in the switch.
