CSE467: Advanced Digital Design
Carl Ebeling, Winter 1999
Welcome to the 467 Home Page
The final exam is Thursday, March 18, 8:30-10:20.
The final project is due Thursday, March 18, at 5:00
Class
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Send email to: your instructor,
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Course Information
Homework Assignments
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Web
Page: due Jan. 8 (4:30 pm)
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Homework
1: due Wednesday, Jan. 13, beginning of class.
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Homework
2: due Friday, Jan. 29, beginning of class.
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Homework
3: due Wednesday, Feb. 17, beginning of class.
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Homework
4: due Monday, March 1, beginning of class.
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Homework
5: due Wednesday, March 10, beginning of class.
Lab Assignments
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Lab policies and hours
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Hardware Lab Web Page
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Lab
1: due Friday, Jan. 15 (by 4:30)
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Lab
2: due Friday, Jan. 29 (by 4:30)
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Lab
3: Simulation due Friday, Feb. 5 (Wednesday section), Wednesday,
Feb. 10 (Monday section)
Working circuit due Friday, Feb. 12 (Wednesday section), Wednesday,
Feb. 17 (Monday section)
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Lab
4: Part 1 due at the end of lab
Part 2 due with Lab 3 circuit
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Lab 5:
Due Feb. 26
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Final Project:
Initial design specification due March 1
Initial schematics/Verilog due March 5
Completed circuit due March 18
Other Information
The CSE467 Web:
Copyright 1996, 1997, 1998, 1999; Department of Computer Science and Engineering,
University of Washington.
Portions of the CSE467 Web may be reprinted or adapted for academic
nonprofit purposes, providing the source is accurately quoted and duly
credited.
Comments to: cse467-TA@cs.washington.edu
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