Week5, Lecture2: Verilog FSMs
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Table of Contents
Verilog FSMs
Parallel versus serial execution
@ inside always blocks
Assignments
Assignments
Finite state machines
Example: Moore machine
Moore reduce 1s (cont’d)
Another way
Another way (con’t)
Example: Mealy machine reduce 1s
Mealy machine reduce 1s (con’t)
Mealy machine reduce 1s again...
If you use always blocks...
1-always Moore FSM (not recommended!)
PPT Slide
Synchronous Mealy FSMs
Parameters customize module instantiation
Parameters choose logic functionality
Parameters cannot generate logic
Author:
Chris Diorio
Email:
diorio@cs.washington.edu
Home Page:
http://www.cs.washington.edu/education/courses/467/99au/