Lab 2  CSE 467

Laboratory Exercise 6
Adders, Subtractors, and Multipliers


For this lab, you should email to Ryan your answers to the questions in the lab write-up.

Part I         Compile the supplied Quartus project, simulate, and run. Answer questions.
Part II         Read and understand.
Part III        Do all and answer questions.
Parts IV, V, VI Read and understand.
Part VII        Compile the supplied Quartus project, simulate, and run. Answer questions.

Now do another version that compares the lpm implementation to a "just do it" Verilog coding style. For example, you can always multiply by writing

assign x = a  * b;

And let the tools figure out the best way to do it. Compare the results in terms
of the number of logic elements (LEs) needed and the circuit fmax.

Part VIII       Do all and answer questions.
Part IX         Do all and answer questions.

Your email to Ryan is due at the start of next week's Lab period.

This may be of help:
Using Library Modules in Verilog Design


Comments to: cse467-webmaster@cs.washington.edu