Senior Projects

Here is a list of projects that I will be sponsoring over the next few months. If you are interested in working on these, please talk to me. I can only accept a limited number of students. Some of these projects may have partial funding. I have *’ed the projects that need to be done first.

BioSim: Accelerating Biochemical Reaction System Simulation

This is a continuation of the successful project implementation from last year. Our goal is an efficient implementation of Gibson’s algorithm, starting with Gillespie and then extending this to Gibson.

BioSim Subprojects

· * Application-specific floating point modules: Add/sub, Multiplication, Division, Log

· Efficient priority queue implementation

Current Students

Jacob Christiansen
Philip Grin

Former Students

Christopher Bradley

Kevin West

Nolan Clark

Porting the Impulse Tools to VirtexIIPro and Wildcard

Impulse has given us a license to their tools, which allow the designer to write C code that is compiled to a combination of hardware and software. We will be evaluating these tools, porting them to work with the PowerPC on the VirtexIIPro FPGA on the ML300 development board. We also plan a port to the WildCard with the PC as host. We will evaluate the tools in the context of these systems using a couple applications. The first is a string matching algorithm that can be used for intrusion detection. The second is an implementation of the Smith-Waterman DNA sequence search algorithm.

Impulse Subprojects

• * MicroBlaze implementation/evaluation/support. Microblaze is a synthesizable core from Xilinx. The current Impulse tools support the Microblaze processor, so our initial bringup will be to test the Impulse tools with MicroBlaze. To do this we will have to learn how to use the MicroBlaze processor.
• Impulse interfaces for the PLB (processor local bus) of the VirtexIIPro.
• String-matching algorithm research/implementation.
• Smith-Waterman algorithm research/implementation.

Current Students

George Huang

Richard Bannon (MicroBlaze)

Oscar Ng

Cheap/Fast FPGA On-Chip Network

The idea here is to implement the absolutely fastest/cheapest on-chip network for an FPGA. The idea is to route data on a packet-switched network instead of on a shared bus. For example, you might break the Virtex1000 into 4 or 8 parts, with each part communicating with the other via the network. You put data, with the destination address, into the network interface, and get data from other nodes from the network interface. The idea is to do this as efficiently as possible so that the network itself doesn’t take up half (or all!) the FPGA.

Current Students