/*
Features
• Pin and Function Compatible with CY7C1019BV33
• High speed
—tAA = 8, 10, 12, 15 ns
• CMOS for optimum speed/power
• Data Retention at 2.0V
• Center power/ground pinout
• Automatic power-down when deselected
• Easy memory expansion with CE and OE options
• Available in 32-pin TSOP II and 400-mil SOJ package
Functional Description
The CY7C1019CV33 is a high-performance CMOS static
RAM organized as 131,072 words by 8 bits. 

Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers. This
device has an automatic power-down feature that significantly
reduces power consumption when deselected.

Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. 

Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location specified
on the address pins (A0 through A16).

Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.

The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1019CV33 is available in a standard 32-pin TSOP
II and 400-mil-wide SOJ.
*/


`timescale 1ns / 100ps	 

module SRAM12NS_MODEL(
	A,
	IO,
	CE,
	WE,
	OE
	);
	
	
	input [16:0]A;
	inout [7:0]IO;
	input CE, WE, OE;
	
	reg [7:0] out;
	
	
	wire read;
	wire write;
	
	assign read = ( !(CE) && !(OE) && WE );
	assign write = ( !(CE) && OE && !(WE) );  
	
	assign IO =  read ? out : 8'bZ;
	
	reg     [7:0]	mem[131071:0];
	
	// corretion: you should be able to hold OE low and
	//  change the address, and 12ns (approx) later,
	//  you should get the new value.  So the model
	//  will reflect this, added A to the always block
	always @(read or A)
		begin
			#3 // data hold from address change
			if( read )
				out <= #9 mem[A];
		end	   					  
	
	// 	
	always @(write)
		begin
			#6 // t_SD data setup to write end
			if( write )
				mem[A] <= #6 IO;  //  12 - t_SD
		end
	
endmodule