Draw a circuit that implements each of the following verilog fragments. Use datapath blocks like registers, 
ALU when possible. If you need a controller, design it with gates and flip-flops. 
Don't worry about bus widths. Try to go for the low cost design, assuming that multiplexors cost less than adders/subtractors (ALUs).

module (z,x,a,b,c, clock);
input [..] b,c,z;
input clock;
output [..] a,x;

----------------------------
assign a = b + c;
assign x = z + b;
---------------------------
reg[..] a, x;
always @(b or c or z) begin
	a = b + c;
	x = z + b;
end
----------------------------
reg[..] a, x;
always @(posedge clock) begin
   a <= b + c;
   x <= z + b;
end
----------------------------
reg[..] a, x;
always @(posedge clock) begin
	if (op == add)
     		a <= b + c;
  	else
     		x <= z - c;
end
----------------------------
reg[..] a, x;
always begin
	@(posedge clock) a <= b + c;
  	@(posedge clock) x <= z + b;
end
----------------------------
reg[..] a, x;
always @(posedge clock) begin
	case (state)
     		0: begin a <= b + c; state = 1; end
     		1: begin x <= z + b; state = 0; end
	endcase
end
---------------------------
reg out;
always @(clock or data) begin
	if (clock)
		out = data;
end
---------------------------
endmodule

module whatisit(clock,A,Result);
input [15:0] A;
input clock;
output[16:0] Result;

reg [16:0] Result;
reg [8:0] tmp;
reg [7:0] Ahigh, Xhigh
reg [15:0] X;

always @(posedge clock) begin
	Ahigh <= A[15:8];
	Xhigh <= X[15:8];
	tmp <= A[7:0] + X[7:0];
	Results <= {(Ahigh+XHigh+tmp[8]),tmp[7:0]};
end

always @(posedge clock) begin
	if (Reset) X = 1;
	else X = {X[14:0],X[8]^X[6]^X[2]};
end

endmodule