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This lab specification is subject to change. The problem presented, and the high level requirements will not change.
This lab is due in class on Monday, February 6
Purpose
Having designed and implemented a protocol to transfer data from the PC to the Xilinx board, you will now have the opportunity to do something with that data. As we are ultimately working towards "accelerating" an MP3 encoder, your first attempt at data processing will be some simple computation the encoder performs.
The Problem
In one stage of encoding, the encoder is given a sequence of bytes where each byte only contains a few interesting bits. In general, this could be as many as 8, but typically it is smaller. In each byte there is a lot of wasted space, namely those bits that are not interesting. The encoder must compress this stream of bytes by removing the uninteresting bits, and packing what is left into a byte stream.
For example, consider the following series of bytes, and their associated interesting bit counts:
| BYTE (binary) | Length | Content |
| 00010111 | 5 | 10111 |
| 00000110 | 3 | 110 |
| 00001001 | 4 | 1001 |
| 00010111 | 6 | 010111 |
| 00010011 | 5 | 10011 |
| 00011100 | 5 | 11100 |
When compressed, the sequence of bytes should look like
| 10111110 | 10010101 | 11100111 | xxxx1100 |
Note that the final byte contains some unused bits. To address this, we can include a final byte containing the number of relevant bits in the last byte of data. In this case, that number would be four.
Given a sequence of bytes DATA, LEN, DATA, LEN, ... it is your responsibility to perform the compression, so that when the PC performs a read, as per the specification , the array returned contains the compressed bytes, as well as the final byte indicating how many bits in the last byte are valid.
What You Are Given
We will provide you with a working solution to lab 2. This solution performs the read and write protocol to specification (as best as I know). You do not need to use this solution, but it shuld not be terribly different from your solutions to lab 2.
We have also provided a version of pportc.exe which will write a series of bytes to the parallel port and expect the appropriate response. This version of the program does not perform a terribly long request sequence, so look for a more complicated version in the future.
Your Job
You are required to implement this functionality in two manners:
- You should write a c program which performs this particular transformation, and establish performance statistics evaluating the time required. Generally speaking, you should test the speed on very large data sets, so that start up times are hidden (LAME performs this operation several times for each output word of data. Generally several million times).
- You must also implement this functionality in hardware. The existing controller will be able to download the data from the PC, at which point the module of your creation should start processing the data. Once it is finished, the controller can release the data to the PC. Some interaction between this new module and the controller will be required.
- You are required to present an analysis of how long your module takes to process data. This analysis should be theoretical in nature; your hardware should take a particular number of clock cycles to compress data, and you should be able to compute this length from your design alone (no Logic Analyser needed).
Turn in Requirements
When turning in documents, try to make sure that they are organised in a manner that is clear and understandable. You will need to turn in
- The functional part of your c program, the testing environment, and output statistics. Is the time taken a function of input bytes alone, or does the distribution of lengths also play a role?
- Design work and Verilog for your module.
- Theoretical analysis of the performance of your module.
Note that this is a two week assignment. There will be a checkpoint at your second lab meeting where you will need to demonstrate you c simulation and high level design work for your module.
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