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This lab is due in class on Monday, January 23
Purpose
The purpose of this lab is principally to familiarise you with the process of logic synthesis. This is the process by which a logic device is taken from the world of pure specification (you have done this) and is mapped to a physical device.
We will continue to use the Xilinx Foundation Series in this lab, but instead of focusing on design, we will work mostly with the implementation step. You will need to implement the read functionality (in design), and then synthesise your design to a working implementation.
What You Are Given
You have the option of continuing on from your design from lab 1, should you choose. Alternatively, we will provide you with a working solution to lab1, for which read is not functional.
If you decide to use you own design: there are a few important modifications that you must make to you high level schematic. It is necessary to put inverters on PWE and PDS. Further, a widget must be introduced to facilitate the successful synthesis of your design. This widget is not online, but will be soon. Don't worry for now, you will get it by/before lab.
Secondly, there is a Visual Studio project called pportc which contains code for interacting with the parallel port. You can most likely run this code out of the box. pportc.exe sends a write request to the parallel port, and then attempts to read back the data. Examining the ProcessData function will tell give you specifics and allow you to test particular values.
Finally, I have captured the circuit we are providing for you. The file is large, so if you are on the other end of a modem, I apologise.
Your Job
You are required to
- First, implement read functionality as per the protocol specification.
- Once you have completed this, you will be required to implement your design, using XFS's implementation phase. To do so, click on the "implementation" button in the main XFS window.
- At this point, it would be prudent to examine the advanced timing analysis. To the right of "implementation" in the XFS main window is another timing simulator. This simulator uses precise information about the Xilinx board and how your design is compiled to provide very accurate simulation results.
- Next, you will want to acquire a Xilinx FPGA board (available in lab). You will connect the card to the PC via the parallel port, switch the switch labelled "prog/port" to prog, and download your implementation to the chip. Once you have done this, flip the aforementioned switch to "port".
- You can now test your chip by compiling and running the pportc project. This program will send data to the parallel port and expect information in return, as per the protocol . The program prints results of the interaction, from which it should be apparent if your implementation is working.
- You can use the Logic Analyser to probe the parallel port signals as pportc.exe is executing. We will show you in lab how to configure the Logic Analyser, and you should capture several tranmissions (perhaps debugging as well).
Turn in Requirements
When turning in documents, try to make sure that they are organised in a manner that is clear and understandable. You will need to turn in
- Design work and documentation. Document the changes required to implement read. Do not redocument your controller unless it has changed substantially. Do document and discuss important decisions you were faced with in this lab.
- A simulation script and waveforms demonstrating the performance of your implemented design using the advanced timing analysis. This is not the same as the simulator you have been using! (Though they do look similar). Make sure to test many possible conditions: multiple writes and reads. (NB: You will almost certainly need to lengthen your clock from its original 10ns period.)
- Output from the program pportc.exe demonstrating success of the implementation phase.
- Output, in the form of a waveform printout, of data captured from the Logic Analyser. This should be the same run that you use for the previous printout.
- Answers and brief discussion of the following questions:
- What happens if we remove the register from PDS in the main schematic?
- What is the minimum clock frequency that your implementation can tolerate? (look at your timing analysis)
- What net has the longest delay? Why would this particular net have a long delay?
- Using the Logic Analyser (the hardware thingy with probes and whatnot) determine the data rate for your implementation. How long does it take (in reality, not simulation) to tranmit and array of a particular size (at least 11 elements )
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