Homework 5 Instructions. Due Friday 1/26/01

Modify pporttest.v and pportvlog.v to use a 16 bit wide RAM instead of an 8 bit wide RAM. The data form the PC still comes and goes one 8-bit byte at a time. The wider RAM will make it possible to process the data more quickly once it is downloaded, but it will make pportctl more complex. Turn in the modified Verilog along with an explanation of why you think it will work.

For Verilog resources check out the CSE370 homepage under tools. And, there are two copies of a Verilog book available in the lab.

Optional, but recommended: install SynaptiCAD Verilogger Pro (see 467 homepage) on your machine at home or in the lab. Follow this sequence to set up a project:

1. Select Verilogger Pro from the startup screen
2. Project --> New HDL Project
3. right mouse click in the project window and select Add HDL File.
   or select Project --> Add HDL File(s)
4. Add pportvlog.v and pporttest.v
5. Build (second yellow button on toolbar, not the one that says TB)
6. Simulate (Green arrow button on toolbar)
7. Check out the waveforms in the waveform viewer.
8. You can add signals in the waveform viewer by drilling down into pporttest.v in the project window and choosing Watch Signal or Watch Component from the right-mouse menu.
9. Modify your verilog and simulate until it works the way you want.

You can zoom in an out in the waveform viewer. And, to really see how the simulator works, try single stepping. If you see something you don't understand...Ask!