Parallel I/O Protocol

There are five important signals on the parallel cable that connects the PC to the HW:

PDATA[7:0]  This is the 8-bit data bus. This lines can be driven by the PC to send data (write) to the prototyping board, and they can be driven by the HW to receive (read) data read from the prototyping board.

WE asserted by the PC to indicate that the software wants to write to the board

RE asserted by the PC to indicate that the software wants to read from the board

REQ asserted by the PC to indicate that PDATA, WE, RE have been setup for a transfer

BSY asserted by the HW to indicate that the transfer is complete

These signals can be used to implement a "4-phase handshake" for data transfer without a clock. Transfers in either direction are always initiated by the PC. Here are the rules for the PC:

1) Clear REQ and tri-state PDATA
2) Wait until !BSY (safe to drive PDATA)
3) Assert RE, WE, PDATA according to the type of transfer that is desired (read or write) then 
4) Set REQ
5) Wait until BSY 
6) Record PDATA if RE

Here are the rules for the hardware:
1) tri-state PDATA and Clear BSY
2) Wait until REQ
3) If WE record PDATA into local memory, else Assert PDATA with data from local memory
4) Set BSY (this is the acknowledgement)
5) Wait until !REQ

This only defines how to transfer one byte. We also need to define a higher level protocol for transferring arrays. We'll make it simple. The first transfer in either direction specifies the number of bytes that will be transferred in that direction. To write {7,8} to the HW, you would have do three parallel port writes: {2,7,8}. In the case of a read, the HW first sends the number of bytes in the outgoing array. The PC must make that many more read requests to get the whole array. The HW keeps track of the position in the array as the data is being read and written.

What you are given

A Xilinx Foundation project archive that contains a starting schematic and simulation script template. Until the project is posted, you can refer to this schematic. In the schematic you will see a local memory to hold data, all of the I/O pin connections that you will need, and some debugging capabilities for routing the data in the memory to 7-segment displays. This schematic is simpler than the one handed out in class, so review it! The project archive also contains a skeleton simulation script called lab1test.cmd that you should modify for your purposes. You can edit this file when you go to simulation mode in the Xilinx tools.

Your Job

Add the state machine  controller to make it all work, and test it with the Xilinx simulator. To do this, push into the PPORTCTL block in the schematic and edit the schematic. You may use any library or LogicBLOX devices for your schematic (look under tools-->LogicBLOX module generator for useful stuff). For this assignment, it is only necessary to implement the controller for writing the data to the memory. We will add reading later.

Turn in

• Your design work and documentation
• Schematic of your design
• Functional (not timing) Simulation script and waveforms to prove that your controller works. You must show the following signals:
  RESET, PDS, PINT (which is RE), PWE, PBSY, AW, ADDR[6:0], PPDATA[7:0], CLK. The bus signals should be shown in one row of the waveform display in HEX notation. The waveforms must demonstrate two complete array write sequences. The array lengths can be short, but they should be at least 2 or 3 items. 

The Foundation tool suite is an industrial strength tool for digital system design and prototyping. It includes design entry (schematic and HDL) simulation, and automated synthesis algorithms to implement your design on FPGAs.   The results of simulation are available as simulation waveforms in a graphics window.  

In addition to this brief lab guide, there is also an on-line documentation and tutorial available under Xilinx Foundation in the start menu.

Start the Xilinx Foundation Tools from the start menu. 

Under the file menu choose "Restore Project" to restore the starting design from the lab1 archive, restore this design to a location on the desktop, Archive your own file server when you log off.  ALWAYS use Archive and Restore to move the design around. Never copy the working directory.

Schematic Based Design:

When entering your design observe the following rules (this has already been done for you for this project).

All input pins have to go through an IPAD then an IBUF.

All output pins have to go through an OPAD then an OBUF.

For system clock signal, use a BUFG instead of a IBUF.

These could be found in the Symbols Tool Box.