CSE467: Advanced Digital Design

Larry Arnstein, Winter 2000

Requesting academic accommodations: If you would like to request academic accommodations due to a disability, please contact Disabled Student Services, 448 Schmitz, 543-8924(V/TDD). If you have a letter from them indicating you have a disability that requires academic accommodations, please present the letter to me so we can discuss the accommodations you might need for class.

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Course Information

Time and Place: MWF 12:30-1:20 - HCK 316
Labs: T 2:30-5:20 | Th 2:30-5:20 - Sieg 327
Staff:

Instructor: Larry Arnstein
TA: Frank McSherry

Hardware laboratory manager: Chris Morgan

Overview
Syllabus
Schedule (find most updates here)
Office hours:

Larry Arnstein - M 4:00pm - 5:00pm, 323D
Frank McSherry - TBA

Students

Lecture Notes...see schedule

Other Resources:

Lecture Notes from Previous Quarters
Verilog HDL Synthesis, A Practical Primer by J. Bhasker. Two copies in the Lab. Please use them there.

Homework Assignments...see schedule

Lab Information and Assignments

Hardware Lab Web Page

Policies and Guidelines
Xilinx Tools
Xilinx Tips (Read this, several times)
XESS documentation
Take home tools Xilinx Book w/ Software or Demo Version of Verilogger Pro by SynaptiCAD.
Hardware platform information: Small System: www.digilent.cc, and large system, the XSV300 board from www.xess.com

Other Information

The CSE467 Web:
Copyright 1996, 1997, 1998, 1999, 2000, 2001; Department of Computer Science and Engineering, University of Washington.

Portions of the CSE467 Web may be reprinted or adapted for academic nonprofit purposes, providing the source is accurately quoted and duly credited.

Comments to: cse467-TA@cs.washington.edu (Last Update: 01/03/00)