1. 
					Intruc-	memory 
					tion	
					refer. 	refer.
	200	repeat: load    x	; 200,   212	; 200, 212
      	201  		add     one	; 201,   213	; 200, 213
     	202 		store   x	; 202,   212
        203     	mul     x	; 203,   212
        204             sub     t	; 204,   211
        205             brpos   exit	; 205
        206             br      repeat	; 206
        207             load    x
        208     exit:   sub     one
        209             store   x
        210             halt
        211     t:      number  58
        212     x:      number  1
        213     one:    number  1

Note that jump instructions don't need to reference the destination address.

(a) 200, 212, 201, 213, 202, 212, 203, 212, 204, 211, 205, 206, 200, 212, 200, 213

(b) (i)  V  tag    data	 V  tag   data
	+-+-----+-------+-+-----+-------+
 slot 0	|1|  ?	|2 words|1|  ?	|2 words|
	+-+-----+-------+-+-----+-------+
      1	|1|  ?	|2 words|1|  ?	|2 words|
	+-+-----+-------+-+-----+-------+
      2	|1|  ?	|2 words|1|  ?	|2 words|
	+-+-----+-------+-+-----+-------+
      3	|1|  ?	|2 words|1|  ?	|2 words|
	+-+-----+-------+-+-----+-------+
(ii) 	      7        2       1
	+-----------+------+------+
	|    tag    | slot |offset|
	+-----------+------+------+
	2 words in 1 block => log2=1 bit is enough
	4 slots => log4=2 bits

(iii) 200=0011001000
      tag=0011001
      slot=00
      offset=0
	+-+-------+--------------+-+-------+--------------+
 slot 0	|1|0011001|load x;add one|0|	   |		  |
	+-+-------+--------------+-+-------+--------------+
 slot 1	|0|       |              |0|	   |		  |
	+-+-------+--------------+-+-------+--------------+
 slot 2	|0|       |              |0|	   |		  |
	+-+-------+--------------+-+-------+--------------+
 slot 3	|0|       |              |0|	   |		  |
	+-+-------+--------------+-+-------+--------------+  

2. (a)
(i)  After A, x=10. After B, x=40.  => x=40
(ii) After B, x=20. After A, x=40.  => x=40
(iii)After a1, R1=5, x=5. After B, x=20.
     Switch to A, R1 is restored 5. After A, x=10  => x=10
(iv) After B3, R1=20, x=5. After A, x=10.
     Switch to B, R1 is restored 20. After B4, x=20  => x=20

(b). 7!/3!4!=35 or 35-2=33

3. 
  loop:	TSB(mutex, loop);
	C.S.
        mutex:=0;

4. The key is that WR will be blocked if one of RDs is in CS. 
   The example looks like:

   RD1	------	  -----    ------------   ------
   RD2      -------   ----------  ---------
   WR   blocked forever

5.
	PRODUCER			    CONSUMER
    loop				loop
 	produce data;	P0		    wait(full);	C1
	wait(mutex);	P1		    wait(mutex);	C2
	wait(empty);	P2		    remove item;	C3
	add item;	P3		    signal(mutex);	C4
	signal(mutex);	P4		    signal(empty);	C5
	signal(full);	P5		end	
    end

    Assume buffer is full and nobody in C.S.
    P0, P1, P2 => P wait for empty and lock mutex
    Switch to C, 
    C1, C2 => C waits for mutex unlocking.
    Deadlock here!