378 Spring 2007 - Midterm

name: __________________________________

email: __________________________________

Puzzle: As you await the start of class, I give you this puzzle to pass the time.  The puzzle is called a “dissection”.  Imagine a square.  Cut the square up into 4 pieces and re-arrange those pieces into an equilateral triangle.

Question 1: __________ of 20
Question 2: __________ of 20
Question 3: __________ of 20
Question 4: __________ of 20
Question 5: __________ of 20

Total: ____________ of 100

Question 1

Write the following function:
	char	Load_byte(unsigned char	*c) { return(*c); }
In MIPS assembly, but the ONLY load instruction you can use is “lw”

#assume address is in $a0
#return in $v0
load_byte: 

       andi    $t0, $a0, 0x3   #get byte address in word
       sub     $t1, $a0, $t0   #create word address
       lw      $v0, 0($t1)     #load word
       sll     $t0, $t0, 3     #multiply byte address by 8
       srlv    $v0, $v0, $t0   #shift loaded word right by (byte address)*8 bits
       andi    $v0, $v0, 0xff  #mask to keep only lowest 8 bits
Question 2

Optimize the following loop:
LOOP:
	LW	$4, 0($5)
	NOP
	NOP
	BEQ	$4, $0, EXIT_LOOP
	NOP
	ADDI	$5, $5, 4
	J	LOOP
	NOP
EXIT_LOOP:

Full credit for making the loop run in 4 cycles.  Half credit for 5.
#notes: $4 contains zero at end of loop, $5 contains address of word containing zero
Start:
       LW      $4, 0($5)
LOOP:
       ADDI    $5, $5, 4
       NOP
       BNE     $4, $0, LOOP
       LW      $4, -4($5)       
End:
       NOP                     #need to wait for LW to complete before we change $4
       ADDI    $5, $5, -4      #put address back since we incremented before doing check for zero
       ADD     $4, $0, $0      #set loaded word back to zero

Question 3
The following is a standard MIPS single cycle datapath. How would you modify this datapath in order to support an Add Immediate and Store instruction? The instruction adds rs to the sign-extended immediate in the instruction and stores the result in memory at address rt (Note: No offset is added to rt). Show the additional components required as well as the control signals that would be needed to add this instruction.

Question 4

The following is a standard MIPS single cycle datapath. How would you modify this datapath in order to support a Load on Equals instruction? This instruction compares rs and the sign extended immediate and only performs a load from memory if rs == sign extended immediate. If a load is performed, the contents of memory at location rt are loaded into register $at. Show the additional components required as well as the control signals that would be needed to add this instruction.

Question 5
Modify the following single-cycle architecture to support a SUBTRACT_AND_BRANCH_IF_WAS_ZERO instruction.  This instruction semantically looks like:
	PC <- Reg[RT] == 0 ? PC + Imm : PC + 4
	Reg[RT] = Reg[RT] - Reg[RS]

SBIZ stands for SUBTRACT_AND_BRANCH_IF_WAS_ZERO instruction and is enabled high when executing in the processor.