20 points total
7.31 (5 points)
Since it said "how frequently you think they would occur", we accepted answers with reasonable (and correct) explanations. If you didn't explain it, here are two accepted answers. The first one is closest to the truth, but the second one is also possible:
Cache, TLB, VM
miss, hit, hit (TLB has higher hit ratio than cache, this expect this case more
frequently than the next)
hit, miss, hit (next case is if TLB misses but cache hits)
miss, miss, hit (less common case is when TLB and cache both miss)
miss, miss, miss (really infrequent case)
- or -
miss, hit, hit
miss, miss, hit (you can argue that TLB and cache misses are correlated; when
TLB misses, data is unlikely to be in the cache. Whether this happens
depends on cache and TLB sizes and parameters)
hit, miss, hit
miss, miss, miss
You should understand that by far the most common case of all of these is when the TLB, cache, and VM all have hits. But this case was not in the table you used for this problem, so you didn't get to list it here.
7.32 (8 points)
16KB=2^14, so 16K pages need 14 bits for an offset inside a page.
The rest of the virtual address is the virtual page index, and it's 40-14 = 26 bits long, for 2^26 page table entries.
Each entry contains 4 bits for valid/protection/dirty information (as given in the problem), and the physical frame number, which is 36-14 = 22 bits long, for a total of 26 bits.
The total page table size is then 26 bits * 2^26 entries = 208 MB
Some of you mentioned that to address the page table (which is in memory), the entry size should be some exact number of bytes (it's 26/8 = 3.25 bytes in this case, so we can make it 4). In this case, the page table comes out to be 2^26 * 4 bytes = 256 MB. This was fine.
7.33 (7 points)
See powerpoint slide #9 for section 9.