This assignment has two parts, a programming part and a set of problems taken from the book. The programming part will give you your last practice in writing assembly language programs; the problem part will give you practice in designing and evaluating caches and page tables. Since this is the last assignment and it is "not small", the cache simulation part will be due its already advertised date (Wednesday, May 30), and you'll have two extra days to do the problem part (Friday, June 1). I would advise, however, trying to get both parts done my May 30, to give you extra time to study for finals.
For this assignment, you will be using SPIM and MIPS assembly language to write a simple trace-driven simulator for assessing cache performance. Trace-driven simulation is a commonly used technique for assessing performance of memory hierarchy designs.
In general, cache simulators work as follows.
Given:
a simulator processes each memory reference, decomposing it into tag, index, and offset components. It then checks whether the reference hits in the appropriate cache. (Note that a cache simulator doesn't actually bring data in or out of its simulated caches; rather, it pretends that it has the data there.) Next, it takes the appropriate action (for example, change valid/dirty bits, replace blocks, etc.) and records the statistics. Finally, a simulator outputs a set of statistics, that can include the read hit ratio, the write hit ratio, the average memory access time, and so forth.
Your assignment will simulate a D-cache only, and will do the following:
The input to your simulator will be:
You will output to the SPIM console:
For the purposes of debugging, you are encouraged to test your program on smaller cache sizes and smaller input traces first. You should construct the smaller traces yourself.
Mark and/or Jon will email turn-in instructions and the name of the trace input file.
Do the following problems from the book.