Reducing the Delay of Branches
A fast equality test is used to compare the register values involved in the branch condition rather than a general comparator
- It does not slow down the ID stage much, if at all, which maintains the cycle time
- The fact that it is an equality test is reflected in the ISA
This early “execution” of the branch means that only the instruction following the branch is in the pipeline
- We only need to flush one part of the pipeline
The branch delay is only 1 cycle! (c.f. 4 cycles on slide 2)