The steps for building a top-level ABEL source that refrences a lower-level schematic source are very much similar to the buiding a top-level ABEL source that refrences another lower-level ABEL source. Here also, the top-level ABEL source makes use of the interface and the functional_block statement.
The syntax of the interface statement is same as before:
module_name interface (inputs->outputs);
Here the module_name is the name of the lower level schematic block and the inputs->outputs are the inputs and ouptuts of the lower-level schematic. Hence a statement of the form
simple interface(A, B -> C);
in the top-level ABEL source means that it is refrencing a lower-level source called simple which in our case is a schematic block symbol. Here also you need not define A, B, and C again in the top-level source using ISTYPE's. Just listing them in the interface statement in enough. Also the inputs and outputs in the interface statement should be listed in the same order as the inputs and outputs listed in the lower-level schematic.
The syntax of the functional_block statement is also same as before:
instance_name functional_block module_name;
Here the module_name is the name of the lower-level schematic block and the instance_name is the name of the instance of the lower-level schematic. Hence the statement of the form
simple_instance0..simple_instance1 functional_block simple;
in the top-level ABEL source creates two instances simple_instance0 and simple_instance1 of the schematic simple.
This process of mapping the inputs and outputs of the lower-level schematic is also very similar to the mapping we saw for lower-level ABEL sources. Once you have the lower-level module instanced in the higher-level module, you must now connect the signals of the lower-level module to the signals of the higher-level module. You need to do this because in your test fixture you can access the inputs and outputs of your top-level sources only. Hence, it is the responsibility of the top-level module to provide the inputs and outputs to any lower-level module that it refrences. These signals can be the inputs and outputs of the higher-level module or if multiple lower-level modules have been declared the signals can also be the inputs and outputs of other module instances. Syntax for connecting the signals for the lower and higher modules is quite similar to C++. Just as in C++ the data variables for a particular object are refrenced by putting a '.' after the instance name for that object, in the same way lower-level module signals are refrenced by putting a '.' after the instance of the lower-level module.
Suppose we have the following declaration in our top-level source:
module top-counter;
interface(clk, rst, I -> c7..c0);
title 'top-level counter'
.....
counter interface (clk, rst -> q7..q0);
cntrl functional_block counter;
...
end
Here counter is our lower-level schematic block with two inputs clk, rst and 7 outputs q7..q0. Then we can connect the signals of "counter" and "top-counter" in the EQUATIONS section in the following way:
EQUATIONS
cntrl.clk = clk;
cntrl.rst = rst;
[c7..c0] = cntrl.[q7..q0];
Notice for the outputs, instead of assigning for each output (c7, c6,.., c0) separately we can group them together by using the '[]' . This saves a lot of time and space.