module counting_student (CLK, load, clear, ENP, ENT, rco, value_out, value_in, NXT);
	input CLK, load, clear, ENP, ENT, NXT;
	input [3:0] value_in;
	output rco;
	output [3:0] value_out;
	reg [3:0] counter;
	reg pulser;
	
	assign value_out = counter;
	assign rco = ENT && (counter == 15);
	
	always @ (posedge CLK)
		begin
			if (~clear)
				//Clear the Counter
			else if (~load)
				//Load the Counter
			else if (ENP & ENT & ~NXT & pulser)
				begin
					//Increment the Counter
					pulser <= 0;
				end
			else if (ENP & ENT & ~NXT & ~pulser);
			else
				begin 
					//Hold the Counter at it's current value
					pulser <= 1;
				end
		end
endmodule