Homework Assignments:
Homework 1 - Due In Class Friday October 10th
Homework 2 - Due In Class Friday October 17th
HW2 solutions
Homework 3 - Due In Class Friday October 24th
Homework 4 - Due In Class Friday October 31st
Homework 5 - Due In Class Wednesday November 26th
Homework 6 - Due In Class Friday December 5th
Homework Grading
Homework will be graded on both effort and correctness. If you find yourself having trouble with a problem write down what you know and how far you were able to get to get partial credit. Solution that are incorrect and show no work will not receive any credit. There will be approximately one problem set assigned per week minus exam weeks and, if reasonable, holiday weeks (i.e. Thanksgiving) for a total of approximately 8 problem sets.
A Note on Homework...
Homework will be due in class on the specified due dates. Problem sets will be posted at least 72 hours after the deadline to accomodate anyone who has obtained an extension. Unless you have obtained an extension or otherwise specified, late homework without obtaining an extension is subject to a late penalty. Come talk to us and we'll negotiate what it is.
If you need an extension, you are required to submit a Shakespearean sonnet explaining why you need an extension BEFORE the homework deadline. Your sonnet must strictly follow the format rules with regards to iambic pentameter and rhymne scheme. If you don't know what the format is, Google it since we will check to make sure your sonnet follows the conventions.
For each homework assignment, please write your name and student ID legibly at the top right corner of at least one side of each sheet of paper you turn in. Also please make sure you staple or paperclip your homework together properly. We're not liable for losing papers that were not properly attached together.
Please complete your homework sets in a legible manner. If we can't decrypt your handwriting we can't grade it or give you credit for it. If you are unsure if your handwriting is legible or not, please consider typesetting your homework.
You are encouraged to collaborate with your peers. We realize that Google and Stack Overflow are very good at solving problems for you; rest assured we can use the Internet too. We tried our best to come up with Google-proof problems.
Lecture Slides From Spring 2014
- Overview, History, Fab
- NMOS and PMOS, CMOS Inverter, Pass Gate, Multiplexer, Delay and Power in CMOS
- Basic gates, building gates in CMOS, Boolean algebra, bubble pushing
- Karnaugh maps
- Multiplexers, Decoders, Timing and Glitches
- Latches and Flip Flops
- Synchronous Logic Design, Finite state machines
- Factored FSMs, Timing of sequential lofic, Intro pipelining
- Verilog 1
- Verilog 2
- Adders, Subtractors, Comparators, ALUs
- Counters, shift registers, memory
- Non-volatile memory
- FPGAs
- MIPS architecture, pt 1
- MIPS architecture, pt 2
- Datapath of single cycle processor
- Control path of single cycle processor
- Multicycle Processor
- Pipelined Processor
- Exceptions. Advanced microarchitecture
- Cache: Direct write, Associative
- Virtual Memory
- Embedded Systems and IO
Past Midterms
Past Finals
CSE352 Hardware Design and Implementation
Important Lab Information
For those of you worried you will not be able to finish the first lab in time: you can work on the lab outside of lab time. Just save your waveforms and the TAs will check them off during lab time. To check off your bread board circuits, for the first lab you can take a video of you going through all of the combinations of the switches for check off points 2 and 4, and the TAs will check that off during the next lab.
Course info
Welcome to the webpage for CSE352 Hardware Design and Implementation for the Autumn 2014 quarter. This website will be updated continuously throughout the quarter so please make sure to check back frequently for assignments, laboratory documents, etc.
Make sure to check the class e-mail archive frequently. Some links
may be inactive until later in the quarter.
If you have any problems with this document or the CSE 352 web, please send an email to the instructor and/or the TAs, or see us during
office hours.
Important Lab Information
TA's will arrive at the lab room (CSE 003) at 3:30, so this week come to the lab at 3:30. If you come early you get get ahead by starting Lab 1. The lab kits are in the black cabinet in the corner labeled "CSE 352 Cabinet".
Course Scheduling Information:
Lecture:
MWF 1030AM-1120AM
234 More Hall
Lab Sections:
Th 230PM-520PM
003 CSE
Instructor
Mark Oskin
Email: oskin@cs.washington.edu
Office Hours: By Appointment
Office: CSE564
TAs
Vladimir Korukov
Email: broham@cs.washington.edu
Office Hours: Wednesday 11:30-12:20
Office: CSE 021
Qingwen Pi
Email: qingwenp@cs.washington.edu
Office Hours: Monday 12:30-1:30
Office: CSE 220
We will cover most of the concepts in Digital Design and Computer Architecture by Harris and Harris.
Digital Design and Computer Architecture
 |
The textbook is available at: Amazon
Note that the above text is second edition. Using the first edition is also okay; the reading sections however may differ in a limited
number of places. If you intend to use the first edition please note the reported errata to date below:
here.
| Mon | Tue | Wed | Thu | Fri |
|---|---|---|---|---|
| 22 Second to Last Day of Summer Break #sadface | 23 Last Day of Summer Break :( | 24 Course Overview Slides Semiconductor Physics |
25 No Lab | 26 MOSFETs, VLSI Reading: DDCA Chapter 1 |
| Mon | Tue | Wed | Thu | Fri |
|---|---|---|---|---|
| 29 CMOS Logic and Gate Implementation |
30 Lab 1 Released |
1 CMOS Logic and Gate Implementation Reading: DDCA 1.7, 2.1, 2.2 |
3 |
2 CMOS Logic and Gate Implementation Reading: DDCA 2.3.-2.5 HW 1 Released |
| 6 Memory Circuits Reading: DDCA 2.7-2.10 |
7Lab 2 Released | 8 Memory Circuits, Pass-gate,
static FF Reading: DDCA 3.1-3.3 |
9 Lab 1 Due @ 5:20PM |
10 Memory Circuit, dynamic FF,
Decoder Reading: DDCA 3.4-3.5 HW1 Due in Lecture HW 2 Released |
| 13 Adders Reading: DDCA 5.2.1, 5.2.2 |
14Lab 3 Released | 15 Carry Lookahead Adders, Multipliers Reading: 5.2.6 |
16 Lab 2 Due @ 5:20 PM |
17 FPGAs Reading: DDCA 5.6.2 HW2 Due In Lecture HW3 Released |
| 20 Verilog Basics Reading: See Piazza |
21Lab 4 Released | 22 Verilog (cont'd) Field Programmable Gates HW2 solutions |
23 Lab 3 Due @ 5:20PM |
24 FPGAs (cont'd) HW3 Due In Lecture HW4 Released |
| 27 Processor Design Reading: DDCA 7.3 |
28Lab 5 Released | 29 Processor Design (cont'd) |
30 |
31 Processor Design (cont'd) HW4 Due In Lecture |
| Mon | Tue | Wed | Thu | Fri |
|---|---|---|---|---|
| 3 Pipeline Processor Design | 4 | 5 Pipeline Processor Design | 6 | 7 MIDTERM EXAM in Class 10:30-11:20AM |
| 10 NO CLASS | 11 VETERANS DAY |
12 NO CLASS Lab 6 Released |
13 Lab 4 Due @ 5:20 PM Lab 5 Due @ 11:59 PM |
14 Pipeline Processor Design |
| 17 Pipeline Processor Design | 18 Lab 7 Released | 19 |
20
Lab 6 Due @ 11:59 PM |
21 |
| 24 | 25 | 26 HW 5 due | 27 THANKSGIVING BREAK | 28 THANKSGIVING BREAK |
| Mon | Tue | Wed | Thu | Fri |
|---|---|---|---|---|
| 1 | 2 | 3 |
4 Lab 7 Due @ 11:59 PM |
5 HW6 due |
| 8 | 9 | 10 | 11 | 12 |
Course Goals
- Understanding digital logic at the gate and switch level including combinational and sequential logic elements
- Understanding clocking methodologies and system timing
- Learning how to specify digital-logic designs and compile these into digital circuit implementations
- Understanding the design and implementation of processor architectures
Course Syllabus
- Introduction to modern digital-logic design
- Combinational logic
- Switch logic and basic gates
- Boolean algebra
- Multilevel networks and transformations
- Programmable logic devices
- Delay and circuit performance
- Case studies
- Sequential logic
- Clocks and timing methodologies
- Registers, register files and memories
- Case studies
- Processor Design
- Arithmetic circuits
- Arithmetic and logic units
- Register and bus structures
- Instruction set implementation
- Memory system
- Pipelining
- Interrupts, memory-mapped I/O and embedded systems concepts
- Computer-aided design tools for logic design
- Schematic entry
- Hardware-description-languages
- Simulation and synthesis
- Practical topics
- Asynchronous inputs and metastability
- Serial and parallel communication
- Memories: RAM and ROM
- FPGA architectures
Workload
The course consists of the following components:
- Lectures: There will be about 30 lectures. Attendance and participation is expected at all of them.
- Laboratory Assignments: The lab assignments will be the focus of the course work and will be where you learn the CAD tools and put together your processor. Lab assignments are not canned. They are open-ended design sessions that will carry over from one week to the next and you will often need more time than the 3 hour lab session to complete your work. Attendance during the scheduled lab time when the TAs are available is very important. Please come to lab prepared so that you get as much done as possible with the extra help. Laboratory assignments will be closely tied to the written homework assignments and are intended to give you a taste of working with real digital hardware. The initial set of labs are to be completed individually. We will let you know later when you may start working with a partner.
- Assignments: Written homework with design problems will be assigned to reinforce class concepts. Many of these will mesh with the lab assignments and will require you to use the CAD design tools.
- Midterm exam: The midterm exam will test your knowledge on the first half of the course. The date, length and scope is being determined.
- Final exam: A two-hour exam during finals week as per the University's final exam schedule.
We will try to ensure that the workload is typical for a four-credit course, namely, nine to twelve hours per week outside of the lectures. If we do not succeed, please let us know in whichever way you feel the most comfortable (person-to-person, e-mail, anonymous feedback) and explain which parts of the course are causing you to spend too much time non-productively.
We have structured the course so that spending an hour or two per day will maximize your efficiency. You will work this way in the real world so you cannot cram a three-month design assignment into the last night, so you may as well work this way now. Plus, you will understand the material better. If you leave the homework for the day before it is due you will not have time to ask questions when (not if) the software misbehaves.
Software tools frequently consume more time then they should. We have designed the assignments to get you up to speed gradually (over the period of a few weeks), but undoubtedly there will be some start-up cost (as with any new tool). Essentially, you are learning a new language, a compiler, and getting familiar with a process. Every tool imposes a certain model. Your frustration can be high until you assimilate that model and learn to use it effectively. Be sure to use the tutorials, and do not spend countless hours making no progress. Ask for help. Remember that these tools are written by engineers for engineers and will not necessarily conform to expectations you may have of consumer-oriented tools such as Word.
Assignments
Assignments are generally due a week after being posted, at the beginning of class on the assigned due date. Homework will no longer be accepted after a solution has been published (usually within 3-4 days). If you cannot hand in an assignment in time, please email the TAs before the assignment deadline to obtain an extension. You are strongly encouraged to review the assignment solutions to ensure you understood all the problems.
Your assignments must be neat and legible. We will not spend time trying to decipher messy work. We urge you to use the graphical and word processing tools that are readily available to you in all the labs in the department. Please make good use of the schematic diagram editor in the tools you'll be using to make neat circuit diagrams to include in your assignments.
Collaboration
Homework assignments: Unless specifically stated otherwise, we encourage collaboration on homework, provided (1) You spend at least 15 minutes on each and every problem alone, before discussing it with others, and (2) You write up each and every problem in your own writing, using your own words, and understand the solution fully. Copying someone else's homework is cheating (see below), as is copying the homework from another source (prior year's notes, etc.). Homework assignments are your chance to practice the concepts and make sure you know them well.
Labs: Unless specifically stated otherwise, the labs are meant to be conducted individually. Make sure you go through each step individually to understand the techniques and challenges behind digital systems design. The final labs on the microprocessor design will be conducted in groups.
Grading (may be revised)
- Midterm: 15%
- Final: 35%
- HW: 10%
- Labs: 40%
Cheating
Cheating is a very serious offense. If you are caught cheating, you can expect a failing grade and initiation of a cheating case in the University system. Basically, cheating is an insult to the instructor, to the department and major program, and most importantly, to you and your fellow students. If you feel that you are having a problem with the material, or don't have time to finish an assignment, or have any number of other reasons to cheat, then talk with the instructor. Just don't cheat.
To avoid creating situations where copying can arise, never e-mail or post your solution files. You can post general questions about interpretation and tool use but limit your comments to these categories. If in doubt about what might constitute cheating, send the instructor email describing the situation.
The Dropbox page is accessible here.
Labs
Chip Map Reference
Another Chipmap
Lab 1 Due Thursday @ 5:20PM 10/9/14
Lab 2 Due Thursday @ 5:20PM 10/16/14
Lab 3 Due Thursday @ 5:20PM 10/23/14
Lab 4 Due Thursday @ 5:20PM 10/30/14
Lab 4 alternative checkoffs
Lab 5 Due Thursday @ 11:59PM 11/13/14
Lab 6 Due Thursday @ 11:59PM 11/20/14
Lab 7 Due Thursday @ 11:59PM 12/4/14
Lab Submission Policy
Labs will be checked off in lab sections and office hours (if held in the lab). Please be prepared when asking for a check off since there may be other students waiting for check off or help in the lab. Labs will generally be due during the last lab section the following week that they are assigned unless otherwise specified. You are free to attend either lab section for check off, however if there are not enough workstations to accomodate everyone, those who are enrolled in the section will be granted priority to the workstations.
Late lab check offs are subject to a 20% late penalty. The final lab assignments towards the end of the class may not be turned in late. The final due date for all lab assignment checkoffs is the last scheduled lab section. Beyond that date, all incomplete checkoffs will receive a score of 0.
Computers
We will be using the Dell PCs located in the Baxter Computer Engineering Laboratory, CSE 003. Please do not eat or drink in the laboratory, and respect both the equipment and your fellow students.
Logic Design Tools
We will be using Active-HDL from Aldec Inc. This tool combines schematics, the Verilog harware description language and simulation into one package. This tool will allow us to design at different levels of abstraction and interfaces to a variety of implementation tools for FPGAs and ASICs. We will be using the Aldec tools for CSE467 and CSE477, so learning it in CSE352 will be valuable for future classes.
Active-HDL from Aldec is installed in the Baxter Laboratory. We will be giving you tutorials for learning Active-HDL. These will be sufficient for this class, but you may want to check out the online documentation as well.
Remote Access
Active-HDL and Quartus are available outside of the 003 laboratory only for students currently enrolled in CSE352. It utilizes a license server on campus so your machine will require reasonable Internet access when you are using the tool. However, we have a limited number of concurrent licenses for this software. It is EXTREMELY IMPORTANT that if you use Active-HDL at home you completely shut down the applications when you are not actively using it so that the license is released for others to use. If you do not, and we have difficulty getting everyone access to the tool because of this, then we will have to limit home use.
If you understand this usage model and are willing to cooperate in making sure that the most students possible can make effective use of the tool, then you can find download instructions here.