Saturday, June 2: HW4 solution is posted.
Wednesday, May 30: HW3 solution is posted.
Monday, May 14: HW4 is posted and due on Monday 21st, 2012.
Tuesday, May 8: Midterm solution is posted. Let us know if you have any questions.
Sunday, April 29: HW2 solution contained an error in Q3. You can check out the corrected version now.
Friday, April 27: HW3 is posted and due on Friday May 4. Submit through Catalyst.
Wednesday, April 25: HW2 solution is posted.
Sunday, April 15: HW2 is posted and due on Friday April 20. Submit through Catalyst.
Sunday, April 15: HW1 solution is posted.
Monday, April 2: HW1 is posted under schedule section.
Monday, April 2: There is no class today.
Welcome to the Spring 2012 CSE 352 – Hardware Design and Implementation
Sorry for the late update! We finnaly geared up and got the website running. We hope that you had a great spring break and ready for this quarter.
The website contains essential (and useful) information for the class. Keep in mind that this document is not static, and that new information will be added over the entire quarter. Make sure to check the class e-mail archive frequently. Some links may be inactive until later in the quarter. If you have any problems with this document or the CSE 352 web, please send an email to the instructor and/or the TAs, or see us during office hours.
Instructor
Mark Oskin Email: oskin@cs.washington.edu Office Hours: 1130-1230 Monday and Wednesday Office: CSE564
TAs
Oliver Johnson Email: oliverj@u.washington.edu Office Hours: 700-800pm Monday @the hardware lab.
Trung Le Email: trungtle@cs.washington.edu Office Hours: 130-230pm Thursday @the hardware lab.
We will cover most of the concepts in Digital Design and Computer Architecture by Harris and Harris.
Digital Design and Computer Architecture
|
The text is available from Amazon. Errata reported to date can be found here.
| Mon | Tue | Wed | Thu | Fri |
|---|---|---|---|---|
| 26 Course Overview and Logistics | 27 | 28 Review of Boolean algebra & logic gates, addition H&H p. 3-16, 20-21, 51-60 | 29 | 30 CMOS logic and the digital abstraction H&H p. 16-19, 22-25, 28-32 |
| Mon | Tue | Wed | Thu | Fri |
|---|---|---|---|---|
| 2 No Class HW1 due on Wednesday, April 11. Solution. | 3 Lab 1: Simple circuits. Intro to Aldec-HDL tool Writeup | 4 Complex logic functions, multiplexers, decoders. | 5 Lab 1: Simple circuits. Intro to Aldec-HDL tool Writeup | 6 Combinational logic details, timing. |
| 9 Combinational logic details, continued. | 10 Lab 2: Simple circuits II Writeup | 11 Register Files, SRAM HW1 is due. | 12 Lab 2: Simple circuits II Writeup | 13 Adders, Flash HW2 due on Friday, April 20. |
| 16 Finish adders. Verilog (VHDL) | 17 Lab 3: Introduction to registers Writeup | 18 Verilog. | 19 Lab 3: Introduction to registers Writeup | 20 Carry look ahead adder. LUT HW2 is due. |
| 23 Combinational and sequential logic | 24 Lab 4: Designs in FPGA Writeup | 25 Combinational and sequential logic | 26 Lab 4: Designs in FPGA Writeup | 27 Combinational and sequential logic HW3 due on Friday, May 4. |
| 30 MIDTERM | 1 Lab 5: Lab 5 - Constructing the Y86 Processor Version 1 Writeup | 2 Y86 architecture | 3 Lab 5: Lab 5 - Constructing the Y86 Processor Version 1 Writeup | 4 Y86 architecture |
| Mon | Tue | Wed | Thu | Fri |
|---|---|---|---|---|
| 7 Y86 architecture | 8 Lab 6: Lab 6 - Constructing the Y86 Processor Version 2 Writeup | 9 Y86 architecture | 10 Lab 6: Lab 6 - Constructing the Y86 Processor Version 2 Writeup | 11 Y86 architecture |
| 14 HW4 due on Monday, May 21. | 15 Lab 7: Constructing the Y86 Processor Version 3 Writeup | 16 Busses, memory and I/O | 17 Lab 7: Constructing the Y86 Processor Version 3 Writeup | 18 Busses, memory and I/O |
| 21 HW 4 is due. | 22 Lab 8: UART Writeup File(s): mmio2.hex.txt | 23 | 24 Lab 8: UART Writeup File(s): mmio2.hex.txt | 25 |
Course Goals
- Understanding digital logic at the gate and switch level including combinational and sequential logic elements
- Understanding clocking methodologies and system timing
- Learning how to specify digital-logic designs and compile these into digital circuit implementations
- Understanding the design and implementation of processor architectures
Course Syllabus
- Introduction to modern digital-logic design
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Combinational logic
- Switch logic and basic gates
- Boolean algebra
- Multilevel networks and transformations
- Programmable logic devices
- Delay and circuit performance
- Case studies
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Sequential logic
- Clocks and timing methodologies
- Registers, register files and memories
- Case studies
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Processor Design
- Arithmetic circuits
- Arithmetic and logic units
- Register and bus structures
- Instruction set implementation
- Memory system
- Pipelining
- Interrupts, memory-mapped I/O and embedded systems concepts
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Computer-aided design tools for logic design
- Schematic entry
- Hardware-description-languages
- Simulation and synthesis
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Practical topics
- Asynchronous inputs and metastability
- Serial and parallel communication
- Memories: RAM and ROM
- FPGA architectures
Workload
The course consists of the following components:
- Lectures: There will be about 30 lectures. Attendance and participation is expected at all of them.
- Laboratory Assignments: The lab assignments will be the focus of the course work and will be where you learn the CAD tools and put together your processor. Lab assignments are not canned. They are open-ended design sessions that will carry over from one week to the next and you will often need more time than the 3 hour lab session to complete your work. Attendance during the scheduled lab time when the TAs are available is very important. Please come to lab prepared so that you get as much done as possible with the extra help. Laboratory assignments will be closely tied to the written homework assignments and are intended to give you a taste of working with real digital hardware. Labs can be worked in pairs or individually.
- Assignments: Written homework with design problems will be assigned to reinforce class concepts. Many of these will mesh with the lab assignments and will require you to use the CAD design tools.
- Final exam: A two-hour exam during finals week as per the University’s final exam schedule.
We will try to ensure that the workload is typical for a four-credit course, namely, nine to twelve hours per week outside of the lectures. If we do not succeed, please let us know in whichever way you feel the most comfortable (person-to-person, e-mail, anonymous feedback) and explain which parts of the course are causing you to spend too much time non-productively.
We have structured the course so that spending an hour or two per day will maximize your efficiency. You will work this way in the real world—you cannot cram a three-month design assignment into the last night—so you may as well work this way now. Plus, you will understand the material better. If you leave the homework for the day before it is due you will not have time to ask questions when (not if) the software misbehaves.
Software tools frequently consume more time then they should. We have designed the assignments to get you up to speed gradually (over the period of a few weeks), but undoubtedly there will be some start-up cost (as with any new tool). Essentially, you are learning a new language, a compiler, and getting familiar with a process. Every tool imposes a certain model. Your frustration can be high until you assimilate that model and learn to use it effectively. Be sure to use the tutorials, and do not spend countless hours making no progress. Ask for help. Remember that these tools are written by engineers for engineers and will not necessarily conform to expectations you may have of consumer-oriented tools such as Word.
Your assignments must be neat and legible. We will not spend time trying to decipher messy work. We urge you to use the graphical and word processing tools that are readily available to you in all the labs in the department. Please make good use of the schematic diagram editor in the tools you'll be using to make neat circuit diagrams to include in your assignments.
Assignments
Weekly assignments are due at the beginning of class on the assigned due date. Homework will no longer be accepted after a solution has been published (usually within a couple of days). You are strongly encouraged to review the assignment solutions to ensure you understood all the problems.
Collaboration
Homework: Unless specifically stated otherwise, we encourage collaboration on homework, provided (1) You spend at least 15 minutes on each and every problem alone, before discussing it with others, and (2) You write up each and every problem in your own writing, using your own words, and understand the solution fully. Copying someone else's homework is cheating (see below), as is copying the homework from another source (prior year's notes, etc.). Homework assignments are your chance to practice the concepts and make sure you know them well.
Grading
Cheating
Cheating is a very serious offense. If you are caught cheating, you can expect a failing grade and initiation of a cheating case in the University system. Basically, cheating is an insult to the instructor, to the department and major program, and most importantly, to you and your fellow students. If you feel that you are having a problem with the material, or don't have time to finish an assignment, or have any number of other reasons to cheat, then talk with the instructor. Just don't cheat.
To avoid creating situations where copying can arise, never e-mail or post your solution files. You can post general questions about interpretation and tool use but limit your comments to these categories. If in doubt about what might constitute cheating, send the instructor email describing the situation.
Discussion board is here.
The dropbox link is here.
Labs
Lab1. Lab2. Lab3. Lab4. Lab5. Lab6. Lab7. Lab8. File(s): mmio2.hex.txt
Computers
We will be using the Dell PCs located in the Baxter Computer Engineering Laboratory, CSE 003. Please do not eat or drink in the laboratory, and respect both the equipment and your fellow students.
Logic Design Tools
We will be using Active-HDL from Aldec Inc. This tool combines schematics, the Verilog harware description language and simulation into one package. This tool will allow us to design at different levels of abstraction and interfaces to a variety of implementation tools for FPGAs and ASICs. We will be using the Aldec tools for CSE467 and CSE477, so learning it in CSE352 will be valuable for future classes.
Active-HDL from Aldec is installed in the Baxter Laboratory. We will be giving you tutorials for learning Active-HDL. These will be sufficient for this class, but you may want to check out the online documentation as well.
Remote Access
Active-HDL and Quartus are available outside of the 003 laboratory only for students currently enrolled in CSE352. It utilizes a license server on campus so your machine will require reasonable Internet access when you are using the tool. However, we have a limited number of concurrent licenses for this software. It is EXTREMELY IMPORTANT that if you use Active-HDL at home you completely shut down the applications when you are not actively using it so that the license is released for others to use. If you do not, and we have difficulty getting everyone access to the tool because of this, then we will have to limit home use.
If you understand this usage model and are willing to cooperate in making sure that the most students possible can make effective use of the tool, then you can find download instructions here.
You can follow the tutorials here. Read tips and hints.